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[Qemu-devel] [PATCH] target-tilegx: Implement v?int_* instructions.
From: |
gang . chen . 5i5j |
Subject: |
[Qemu-devel] [PATCH] target-tilegx: Implement v?int_* instructions. |
Date: |
Fri, 2 Oct 2015 11:02:01 +0800 |
From: Chen Gang <address@hidden>
Signed-off-by: Chen Gang <address@hidden>
---
target-tilegx/helper.h | 5 ++++
target-tilegx/simd_helper.c | 56 +++++++++++++++++++++++++++++++++++++++++++++
target-tilegx/translate.c | 14 ++++++++++++
3 files changed, 75 insertions(+)
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index dc865bb..3f4fa3c 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -10,6 +10,11 @@ DEF_HELPER_FLAGS_3(cmula, TCG_CALL_NO_RWG_SE, i64, i64, i64,
i64)
DEF_HELPER_FLAGS_3(cmulaf, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_4(cmul2, TCG_CALL_NO_RWG_SE, i64, i64, i64, int, int)
+DEF_HELPER_FLAGS_2(v1int_h, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v1int_l, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v2int_h, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v2int_l, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+
DEF_HELPER_FLAGS_2(v1multu, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c
index 23c20bd..6fa6318 100644
--- a/target-tilegx/simd_helper.c
+++ b/target-tilegx/simd_helper.c
@@ -102,3 +102,59 @@ uint64_t helper_v2shrs(uint64_t a, uint64_t b)
}
return r;
}
+
+uint64_t helper_v1int_h(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0, tmp;
+ int i;
+
+ for (i = 0; i < 32; i += 8) {
+ tmp = (uint8_t)(a >> (i + 32));
+ r |= tmp << (2 * i + 8);
+ tmp = (uint8_t)(b >> (i + 32));
+ r |= tmp << 2 * i;
+ }
+ return r;
+}
+
+uint64_t helper_v1int_l(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0, tmp;
+ int i;
+
+ for (i = 0; i < 32; i += 8) {
+ tmp = (uint8_t)(a >> i);
+ r |= tmp << (2 * i + 8);
+ tmp = (uint8_t)(b >> i);
+ r |= tmp << 2 * i;
+ }
+ return r;
+}
+
+uint64_t helper_v2int_h(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0, tmp;
+ int i;
+
+ for (i = 0; i < 32; i += 16) {
+ tmp = (uint16_t)(a >> (i + 32));
+ r |= tmp << (2 * i + 16);
+ tmp = (uint16_t)(b >> (i + 32));
+ r |= tmp << 2 * i;
+ }
+ return r;
+}
+
+uint64_t helper_v2int_l(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0, tmp;
+ int i;
+
+ for (i = 0; i < 32; i += 16) {
+ tmp = (uint16_t)(a >> i);
+ r |= tmp << (2 * i + 16);
+ tmp = (uint16_t)(b >> i);
+ r |= tmp << 2 * i;
+ }
+ return r;
+}
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 03c8e76..6853628 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1334,10 +1334,17 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
unsigned opext,
case OE_RRR(V1DOTPUS, 0, X0):
case OE_RRR(V1DOTPU, 0, X0):
case OE_RRR(V1DOTP, 0, X0):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V1INT_H, 0, X0):
case OE_RRR(V1INT_H, 0, X1):
+ gen_helper_v1int_h(TDEST, tsrca, tsrcb);
+ mnemonic = "v1int_h";
+ break;
case OE_RRR(V1INT_L, 0, X0):
case OE_RRR(V1INT_L, 0, X1):
+ gen_helper_v1int_l(TDEST, tsrca, tsrcb);
+ mnemonic = "v1int_l";
+ break;
case OE_RRR(V1MAXU, 0, X0):
case OE_RRR(V1MAXU, 0, X1):
case OE_RRR(V1MINU, 0, X0):
@@ -1403,10 +1410,17 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
unsigned opext,
case OE_RRR(V2CMPNE, 0, X1):
case OE_RRR(V2DOTPA, 0, X0):
case OE_RRR(V2DOTP, 0, X0):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V2INT_H, 0, X0):
case OE_RRR(V2INT_H, 0, X1):
+ gen_helper_v2int_h(TDEST, tsrca, tsrcb);
+ mnemonic = "v2int_h";
+ break;
case OE_RRR(V2INT_L, 0, X0):
case OE_RRR(V2INT_L, 0, X1):
+ gen_helper_v2int_l(TDEST, tsrca, tsrcb);
+ mnemonic = "v2int_l";
+ break;
case OE_RRR(V2MAXS, 0, X0):
case OE_RRR(V2MAXS, 0, X1):
case OE_RRR(V2MINS, 0, X0):
--
1.9.3
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