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[Qemu-devel] [PULL 07/12] target-i386: add ABM to Haswell* and Broadwell
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [PULL 07/12] target-i386: add ABM to Haswell* and Broadwell* CPU models |
Date: |
Mon, 5 Oct 2015 13:06:29 -0300 |
From: Paolo Bonzini <address@hidden>
ABM is only implemented as a single instruction set by AMD; all AMD
processors support both instructions or neither. Intel considers POPCNT
as part of SSE4.2, and LZCNT as part of BMI1, but Intel also uses AMD's
ABM flag to indicate support for both POPCNT and LZCNT. It has to be
added to Haswell and Broadwell because Haswell, by adding LZCNT, has
completed the ABM.
Tested with "qemu-kvm -cpu Haswell-noTSX,enforce" (and also with older
machine types) on an Haswell-EP machine.
Signed-off-by: Paolo Bonzini <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>
---
include/hw/i386/pc.h | 22 +++++++++++++++++++++-
target-i386/cpu.c | 8 ++++----
2 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index c13e91d..8662a29 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -298,7 +298,27 @@ int e820_get_num_entries(void);
bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
#define PC_COMPAT_2_4 \
- HW_COMPAT_2_4
+ HW_COMPAT_2_4 \
+ {\
+ .driver = "Haswell-" TYPE_X86_CPU,\
+ .property = "abm",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Haswell-noTSX-" TYPE_X86_CPU,\
+ .property = "abm",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Broadwell-" TYPE_X86_CPU,\
+ .property = "abm",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Broadwell-noTSX-" TYPE_X86_CPU,\
+ .property = "abm",\
+ .value = "off",\
+ },
#define PC_COMPAT_2_3 \
PC_COMPAT_2_4 \
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 6cccc77..21bad59 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1081,7 +1081,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_LAHF_LM,
+ CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
@@ -1116,7 +1116,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_LAHF_LM,
+ CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
@@ -1153,7 +1153,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
+ CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
@@ -1191,7 +1191,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
+ CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
--
2.1.0
- [Qemu-devel] [PULL 00/12] X86 queue, 2015-10-05, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 12/12] icc_bus: drop the unused files, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 01/12] cpu: Introduce X86CPUTopoInfo structure for argument simplification, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 03/12] target-i386: Convert kvm_default_*features to property/value pairs, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 04/12] target-i386: Move breakpoint related functions to new file, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 07/12] target-i386: add ABM to Haswell* and Broadwell* CPU models,
Eduardo Habkost <=
- [Qemu-devel] [PULL 06/12] target-i386: get/put MSR_TSC_AUX across reset and migration, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 09/12] apic: move APIC's MMIO region mapping into APIC, Eduardo Habkost, 2015/10/08
- Re: [Qemu-devel] [PULL 00/12] X86 queue, 2015-10-05, Peter Maydell, 2015/10/08
- [Qemu-devel] [PULL 08/12] Correctly re-init EFER state during INIT IPI, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 02/12] vl: Add another sanity check to smp_parse() function, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 10/12] x86: use new method to correct reset sequence, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 05/12] target-i386: Make check_hw_breakpoints static, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 11/12] cpu/apic: drop icc bus/bridge, Eduardo Habkost, 2015/10/08