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[Qemu-devel] [PATCH v4 06/26] target-arm: Add condexec state to insn_sta
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v4 06/26] target-arm: Add condexec state to insn_start |
Date: |
Wed, 30 Sep 2015 15:09:26 +1000 |
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-arm/cpu.h | 1 +
target-arm/translate-a64.c | 2 +-
target-arm/translate.c | 3 ++-
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index cc1578c..cebd463 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -95,6 +95,7 @@
struct arm_boot_info;
#define NB_MMU_MODES 7
+#define TARGET_INSN_START_EXTRA_WORDS 1
/* We currently assume float and double are IEEE single and double
precision respectively.
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index bc2040e..654a586 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -11090,7 +11090,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
tcg_ctx.gen_opc_instr_start[lj] = 1;
tcg_ctx.gen_opc_icount[lj] = num_insns;
}
- tcg_gen_insn_start(dc->pc);
+ tcg_gen_insn_start(dc->pc, 0);
num_insns++;
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 44468dc..fb69ecb 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -11317,7 +11317,8 @@ static inline void
gen_intermediate_code_internal(ARMCPU *cpu,
tcg_ctx.gen_opc_instr_start[lj] = 1;
tcg_ctx.gen_opc_icount[lj] = num_insns;
}
- tcg_gen_insn_start(dc->pc);
+ tcg_gen_insn_start(dc->pc,
+ (dc->condexec_cond << 4) | (dc->condexec_mask >>
1));
num_insns++;
#ifdef CONFIG_USER_ONLY
--
2.4.3
- [Qemu-devel] [PATCH v4 09/26] target-s390x: Add cc_op state to insn_start, (continued)
- [Qemu-devel] [PATCH v4 09/26] target-s390x: Add cc_op state to insn_start, Richard Henderson, 2015/10/08
- [Qemu-devel] [PATCH v4 13/26] target-sparc: Split out gen_branch_n, Richard Henderson, 2015/10/08
- [Qemu-devel] [PATCH v4 16/26] tcg: Merge cpu_gen_code into tb_gen_code, Richard Henderson, 2015/10/08
- [Qemu-devel] [PATCH v4 19/26] tcg: Pass data argument to restore_state_to_opc, Richard Henderson, 2015/10/08
- [Qemu-devel] [PATCH v4 20/26] tcg: Save insn data and use it in cpu_restore_state_from_tb, Richard Henderson, 2015/10/08
- [Qemu-devel] [PATCH v4 18/26] tcg: Add TCG_MAX_INSNS, Richard Henderson, 2015/10/08
- [Qemu-devel] [PATCH v4 22/26] tcg: Remove tcg_gen_code_search_pc, Richard Henderson, 2015/10/08
- Re: [Qemu-devel] [PATCH v4 00/26] Do away with TB retranslation, Aurelien Jarno, 2015/10/08
- [Qemu-devel] [PATCH v4 03/26] target-*: Increment num_insns immediately after tcg_gen_insn_start, Richard Henderson, 2015/10/08
- [Qemu-devel] [PATCH v4 05/26] tcg: Allow extra data to be attached to insn_start, Richard Henderson, 2015/10/08
- [Qemu-devel] [PATCH v4 06/26] target-arm: Add condexec state to insn_start,
Richard Henderson <=
- [Qemu-devel] [PATCH v4 08/26] target-mips: Add delayed branch state to insn_start, Richard Henderson, 2015/10/08
- [Qemu-devel] [PATCH v4 11/26] target-cris: Mirror gen_opc_pc into insn_start, Richard Henderson, 2015/10/08
- [Qemu-devel] [PATCH v4 24/26] tcg: Allocate a guard page after code_gen_buffer, Richard Henderson, 2015/10/08
- [Qemu-devel] [PATCH v4 15/26] target-sparc: Add npc state to insn_start, Richard Henderson, 2015/10/08
- [Qemu-devel] [PATCH v4 21/26] tcg: Remove gen_intermediate_code_pc, Richard Henderson, 2015/10/08