[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH QEMU] target-arm: Add support for SPSR_(ABT|UND|IRQ|
From: |
Soren Brinkmann |
Subject: |
[Qemu-devel] [PATCH QEMU] target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ) |
Date: |
Wed, 14 Oct 2015 21:41:08 -0700 |
Signed-off-by: Soren Brinkmann <address@hidden>
---
Hi,
I recently came across some code that caused undefined instruction exceptions
when executing instructions 'mrs x11, spsr_abt' and the like. I'm not sure I
get the full picture, but it seems QEMU already keeps the state for those SPSR
registers and all that might be missing is exposing those registers to the
guest.
Thanks,
Sören
target-arm/helper.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 83679970b432..0c64c0588115 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3281,6 +3281,22 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.type = ARM_CP_ALIAS,
.opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
.access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
+ { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_ALIAS,
+ .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[4]) },
+ { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_ALIAS,
+ .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[2]) },
+ { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_ALIAS,
+ .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[3]) },
+ { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_ALIAS,
+ .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[5]) },
{ .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
.access = PL2_RW, .writefn = vbar_write,
--
2.6.1.3.g59394a9
- [Qemu-devel] [PATCH QEMU] target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ),
Soren Brinkmann <=