[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 2/2] target-xtensa: implement S32NB
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH 2/2] target-xtensa: implement S32NB |
Date: |
Wed, 14 Oct 2015 08:54:28 +0300 |
S32NB provides the same functionality as S32I with two exceptions.
First, when its operation leaves the processor, the external transaction
is marked Non-Bufferable. Second, it may not be used to write to
Instruction RAM.
In QEMU S32NB is equivalent to S32I.
Signed-off-by: Max Filippov <address@hidden>
---
target-xtensa/translate.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index cd2148e..9b6033d 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -1963,6 +1963,17 @@ static void disas_xtensa_insn(CPUXtensaState *env,
DisasContext *dc)
}
break;
+ case 5: /*S32N*/
+ if (gen_window_check2(dc, RRI4_S, RRI4_T)) {
+ TCGv_i32 addr = tcg_temp_new_i32();
+
+ tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2);
+ gen_load_store_alignment(dc, 2, addr, false);
+ tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring);
+ tcg_temp_free(addr);
+ }
+ break;
+
default:
RESERVED();
break;
--
1.8.1.4