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Re: [Qemu-devel] [PATCH] target-mips: Add more reg numbers for RDHWR
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From: |
Leon Alrae |
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Subject: |
Re: [Qemu-devel] [PATCH] target-mips: Add more reg numbers for RDHWR |
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Date: |
Fri, 16 Oct 2015 15:53:05 +0100 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 |
On 05/10/15 13:48, Yongbok Kim wrote:
> Add more register numbers for RDHWR
Could the commit message say which registers exactly this patch is adding?
> Add check_hwrena() to simplify access control checkings.
> Add RDHWR support to microMIPS R6
>
> Signed-off-by: Yongbok Kim <address@hidden>
> ---
> @@ -1357,6 +1357,12 @@ void helper_mtc0_hwrena(CPUMIPSState *env,
> target_ulong arg1)
> {
> uint32_t mask = 0x0000000F;
>
> + if (env->CP0_Config1 & (1 << CP0C1_PC)) {
> + mask |= (1 << 4);
> + }
I think we should check also for ISA_MIPS32R6 here. The access to
CP0.PerfCnt via RDHWR was added in R6 and before that the register
number 4 in HWREna was reserved.
Otherwise looks good to me.
Thanks,
Leon