Re: [Qemu-devel] [PATCH 4/4] mips: add gic support to malta

[Leon Alrae]

On 16/10/15 00:52, Yongbok Kim wrote:
>      /*
>       * We have a circular dependency problem: pci_bus depends on isa_irq,
>       * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
> @@ -1155,7 +1218,11 @@ void mips_malta_init(MachineState *machine)
>  
>      /* Interrupt controller */
>      /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
> -    s->i8259 = i8259_init(isa_bus, env->irq[2]);
> +    if (env->gic_irqs) {
> +        s->i8259 = i8259_init(isa_bus, env->gic_irqs[3]);

Probably s->gic.gic_irqs[3].irq should be used here.

BTW I think "gic_irqs" can be replaced with a better name, something
like "irq_state".

> +    } else {
> +        s->i8259 = i8259_init(isa_bus, env->irq[2]);
> +    }
>  
>      isa_bus_irqs(isa_bus, s->i8259);
>      pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> @@ -1209,7 +1276,7 @@ static void mips_malta_machine_init(MachineClass *mc)
>  {
>      mc->desc = "MIPS Malta Core LV";
>      mc->init = mips_malta_init;
> -    mc->max_cpus = 16;
> +    mc->max_cpus = 32;
>      mc->is_default = 1;
>  }
>  
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index 639ef37..fdd5643 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -594,6 +594,7 @@ struct CPUMIPSState {
>  
>      const mips_def_t *cpu_model;
>      void *irq[8];
> +    void **gic_irqs;

I don't think CPUMIPSState need any information about gic external
interrupts.

Leon

>      QEMUTimer *timer; /* Internal timer */
>  };
>  
>