Re: [Qemu-devel] [PATCH 0/4] mips: add Global Interrupt Controller

[Peter Crosthwaite]

On Thu, Oct 15, 2015 at 4:52 PM, Yongbok Kim <address@hidden> wrote:
> Add support of MIPS GIC.
> The patchset implements the Global Interrupt Controller.
>
> With the patchset Linux Kernel detects GIC and utilises it.
> # cat /proc/interrupts
>            CPU0
>   0:          2    XT-PIC   0  timer
>   2:          0    XT-PIC   2  cascade
>   4:        462    XT-PIC   4  serial
>   8:          0    XT-PIC   8  rtc0
>  11:          0    XT-PIC  11  uhci_hcd:usb1
>  14:       1026    XT-PIC  14  ide0
>  15:          0    XT-PIC  15  ide1
>  21:          0      MIPS   5  CoreHi
>  23:         44      MIPS   7  timer
>  25:      12290  MIPS GIC Local   1  timer
>  34:       1490  MIPS GIC  10  XT-PIC cascade
>  98:       1490  MIPS GIC  74
> ERR:          0
>
> Limitation:
> Level triggering only
> No User-Mode Visible Section
> GIC CounterHi not implemented (Countbits = 32bits)
> DINT not implemented
> Local WatchDog, Fast Debug Channel, Perf Counter not implemented
>
> It is based on the earlier un-merged GIC implementation.
> https://lists.gnu.org/archive/html/qemu-devel/2013-03/msg00194.html
>
> For more information,
> http://imgtec.com/mips/warrior/p-class-p5600-multiprocessor-core/
> http://imgtec.com/mips/warrior/i-class-i6400-multiprocessor-core/
>
>
> Yongbok Kim (4):
>   target-mips: add CMGCRBase register
>   mips: add Global Config Register block (part)
>   mips: add Global Interrupt Controller
>   mips: add gic support to malta
>
>  hw/mips/Makefile.objs        |    2 +-
>  hw/mips/mips_gcr.c           |  120 ++++++++
>  hw/mips/mips_gcr.h           |   57 ++++
>  hw/mips/mips_gic.c           |  653 
> ++++++++++++++++++++++++++++++++++++++++++
>  hw/mips/mips_gic.h           |  298 +++++++++++++++++++

New interrupt controllers should go in the hw/intc directory. GCR
probably belongs in misc (there are similar concepts there for other
arches like arm_sysctl).

Regards,
Peter

>  hw/mips/mips_malta.c         |   71 +++++-
>  target-mips/cpu.h            |    4 +-
>  target-mips/translate.c      |   17 ++
>  target-mips/translate_init.c |    3 +-
>  9 files changed, 1220 insertions(+), 5 deletions(-)
>  create mode 100644 hw/mips/mips_gcr.c
>  create mode 100644 hw/mips/mips_gcr.h
>  create mode 100644 hw/mips/mips_gic.c
>  create mode 100644 hw/mips/mips_gic.h
>
>