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[Qemu-devel] [PATCH v5 01/14] target-arm: Add HPFAR_EL2
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v5 01/14] target-arm: Add HPFAR_EL2 |
Date: |
Mon, 26 Oct 2015 14:01:54 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 12 ++++++++++++
2 files changed, 13 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 3daa7f5..7d3c4c7 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -279,6 +279,7 @@ typedef struct CPUARMState {
};
uint64_t far_el[4];
};
+ uint64_t hpfar_el2;
union { /* Translation result. */
struct {
uint64_t _unused_par_0;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e7fda37..3aec303 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3230,6 +3230,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
{ .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
+ .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
REGINFO_SENTINEL
};
@@ -3460,6 +3464,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
.access = PL2_RW, .resetvalue = 0,
.fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
+ { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
+ .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
+ .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
+ { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
+ .access = PL2_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
REGINFO_SENTINEL
};
--
1.9.1
- [Qemu-devel] [PATCH v5 00/14] arm: Steps towards EL2 support round 5, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 02/14] target-arm: lpae: Make t0sz and t1sz signed integers, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 01/14] target-arm: Add HPFAR_EL2,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v5 03/14] target-arm: lpae: Move declaration of t0sz and t1sz, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 05/14] target-arm: lpae: Replace tsz with computed inputsize, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 04/14] target-arm: Add support for AArch32 S2 negative t0sz, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 06/14] target-arm: lpae: Rename granule_sz to stride, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 07/14] target-arm: Add computation of starting level for S2 PTW, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 08/14] target-arm: Add support for S2 page-table protection bits, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 09/14] target-arm: Avoid inline for get_phys_addr, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 10/14] target-arm: Add ARMMMUFaultInfo, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 11/14] target-arm: Add S2 translation to 64bit S1 PTWs, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 13/14] target-arm: Route S2 MMU faults to EL2, Edgar E. Iglesias, 2015/10/26