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[Qemu-devel] [PULL 12/27] i.MX: Standardize i.MX EPIT debug
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/27] i.MX: Standardize i.MX EPIT debug |
Date: |
Tue, 27 Oct 2015 14:33:14 +0000 |
From: Jean-Christophe Dubois <address@hidden>
The goal is to have debug code always compiled during build.
We standardize all debug output on the following format:
[QOM_TYPE_NAME]reporting_function: debug message
We also replace IPRINTF with qemu_log_mask(). The qemu_log_mask() output
is following the same format as the above debug.
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/timer/imx_epit.c | 48 ++++++++++++++++++++----------------------------
1 file changed, 20 insertions(+), 28 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 9649851..967be4a 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -16,8 +16,17 @@
#include "hw/misc/imx_ccm.h"
#include "qemu/main-loop.h"
-#define DEBUG_TIMER 0
-#if DEBUG_TIMER
+#ifndef DEBUG_IMX_EPIT
+#define DEBUG_IMX_EPIT 0
+#endif
+
+#define DPRINTF(fmt, args...) \
+ do { \
+ if (DEBUG_IMX_EPIT) { \
+ fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_EPIT, \
+ __func__, ##args); \
+ } \
+ } while (0)
static char const *imx_epit_reg_name(uint32_t reg)
{
@@ -37,24 +46,6 @@ static char const *imx_epit_reg_name(uint32_t reg)
}
}
-# define DPRINTF(fmt, args...) \
- do { fprintf(stderr, "%s: " fmt , __func__, ##args); } while (0)
-#else
-# define DPRINTF(fmt, args...) do {} while (0)
-#endif
-
-/*
- * Define to 1 for messages about attempts to
- * access unimplemented registers or similar.
- */
-#define DEBUG_IMPLEMENTATION 1
-#if DEBUG_IMPLEMENTATION
-# define IPRINTF(fmt, args...) \
- do { fprintf(stderr, "%s: " fmt, __func__, ##args); } while (0)
-#else
-# define IPRINTF(fmt, args...) do {} while (0)
-#endif
-
/*
* Exact clock frequencies vary from board to board.
* These are typical.
@@ -136,9 +127,8 @@ static uint64_t imx_epit_read(void *opaque, hwaddr offset,
unsigned size)
{
IMXEPITState *s = IMX_EPIT(opaque);
uint32_t reg_value = 0;
- uint32_t reg = offset >> 2;
- switch (reg) {
+ switch (offset >> 2) {
case 0: /* Control Register */
reg_value = s->cr;
break;
@@ -161,11 +151,12 @@ static uint64_t imx_epit_read(void *opaque, hwaddr
offset, unsigned size)
break;
default:
- IPRINTF("Bad offset %x\n", reg);
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
+ HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset);
break;
}
- DPRINTF("(%s) = 0x%08x\n", imx_epit_reg_name(reg), reg_value);
+ DPRINTF("(%s) = 0x%08x\n", imx_epit_reg_name(offset >> 2), reg_value);
return reg_value;
}
@@ -190,12 +181,12 @@ static void imx_epit_write(void *opaque, hwaddr offset,
uint64_t value,
unsigned size)
{
IMXEPITState *s = IMX_EPIT(opaque);
- uint32_t reg = offset >> 2;
uint64_t oldcr;
- DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(reg), (uint32_t)value);
+ DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2),
+ (uint32_t)value);
- switch (reg) {
+ switch (offset >> 2) {
case 0: /* CR */
oldcr = s->cr;
@@ -271,7 +262,8 @@ static void imx_epit_write(void *opaque, hwaddr offset,
uint64_t value,
break;
default:
- IPRINTF("Bad offset %x\n", reg);
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
+ HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset);
break;
}
--
1.9.1
- [Qemu-devel] [PULL 16/27] target-arm: lpae: Move declaration of t0sz and t1sz, (continued)
- [Qemu-devel] [PULL 16/27] target-arm: lpae: Move declaration of t0sz and t1sz, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 21/27] target-arm: Add support for S2 page-table protection bits, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 20/27] target-arm: Add computation of starting level for S2 PTW, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 01/27] target-arm: Fix "no 64-bit EL2" assumption in arm_excp_unmasked(), Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 07/27] i.MX: Standardize i.MX GPIO debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 10/27] i.MX: Standardize i.MX CCM debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 05/27] hw/arm/virt: don't use a15memmap directly, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 03/27] target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ), Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 04/27] arm_gic_kvm: Disable live migration if not supported, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 15/27] target-arm: lpae: Make t0sz and t1sz signed integers, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 12/27] i.MX: Standardize i.MX EPIT debug,
Peter Maydell <=
- [Qemu-devel] [PULL 18/27] target-arm: lpae: Replace tsz with computed inputsize, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 06/27] i.MX: Standardize i.MX serial debug., Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 22/27] target-arm: Avoid inline for get_phys_addr, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 08/27] i.MX: Standardize i.MX I2C debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 02/27] target-arm/translate.c: Handle non-executable page-straddling Thumb insns, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 09/27] i.MX: Standardize i.MX AVIC debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 11/27] i.MX: Standardize i.MX FEC debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 27/27] target-arm: Add support for S1 + S2 MMU translations, Peter Maydell, 2015/10/27
- Re: [Qemu-devel] [PULL 00/27] target-arm queue, Peter Maydell, 2015/10/27