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[Qemu-devel] [PULL 06/27] i.MX: Standardize i.MX serial debug.
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 06/27] i.MX: Standardize i.MX serial debug. |
Date: |
Tue, 27 Oct 2015 14:33:08 +0000 |
From: Jean-Christophe Dubois <address@hidden>
The goal is to have debug code always compiled during build.
We standardize all debug output on the following format:
[QOM_TYPE_NAME]reporting_function: debug message
We also replace IPRINTF with qemu_log_mask(). The qemu_log_mask() output
is following the same format as the above debug.
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/char/imx_serial.c | 51 +++++++++++++++++++++++++--------------------------
1 file changed, 25 insertions(+), 26 deletions(-)
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index f0c4c72..45cf00d 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -22,25 +22,17 @@
#include "sysemu/sysemu.h"
#include "sysemu/char.h"
-//#define DEBUG_SERIAL 1
-#ifdef DEBUG_SERIAL
-#define DPRINTF(fmt, args...) \
-do { printf("%s: " fmt , TYPE_IMX_SERIAL, ##args); } while (0)
-#else
-#define DPRINTF(fmt, args...) do {} while (0)
+#ifndef DEBUG_IMX_UART
+#define DEBUG_IMX_UART 0
#endif
-/*
- * Define to 1 for messages about attempts to
- * access unimplemented registers or similar.
- */
-//#define DEBUG_IMPLEMENTATION 1
-#ifdef DEBUG_IMPLEMENTATION
-# define IPRINTF(fmt, args...) \
- do { fprintf(stderr, "%s: " fmt, TYPE_IMX_SERIAL, ##args); } while (0)
-#else
-# define IPRINTF(fmt, args...) do {} while (0)
-#endif
+#define DPRINTF(fmt, args...) \
+ do { \
+ if (DEBUG_IMX_UART) { \
+ fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \
+ __func__, ##args); \
+ } \
+ } while (0)
static const VMStateDescription vmstate_imx_serial = {
.name = TYPE_IMX_SERIAL,
@@ -115,7 +107,8 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
IMXSerialState *s = (IMXSerialState *)opaque;
uint32_t c;
- DPRINTF("read(offset=%x)\n", offset >> 2);
+ DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset);
+
switch (offset >> 2) {
case 0x0: /* URXD */
c = s->readbuff;
@@ -167,7 +160,8 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
return 0x0; /* TODO */
default:
- IPRINTF("%s: bad offset: 0x%x\n", __func__, (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
+ HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
return 0;
}
}
@@ -178,9 +172,8 @@ static void imx_serial_write(void *opaque, hwaddr offset,
IMXSerialState *s = (IMXSerialState *)opaque;
unsigned char ch;
- DPRINTF("write(offset=%x, value = %x) to %s\n",
- offset >> 2,
- (unsigned int)value, s->chr ? s->chr->label : "NODEV");
+ DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n",
+ offset, (unsigned int)value, s->chr ? s->chr->label : "NODEV");
switch (offset >> 2) {
case 0x10: /* UTXD */
@@ -198,7 +191,9 @@ static void imx_serial_write(void *opaque, hwaddr offset,
case 0x20: /* UCR1 */
s->ucr1 = value & 0xffff;
+
DPRINTF("write(ucr1=%x)\n", (unsigned int)value);
+
imx_update(s);
break;
@@ -266,12 +261,14 @@ static void imx_serial_write(void *opaque, hwaddr offset,
case 0x2d: /* UTS1 */
case 0x23: /* UCR4 */
- IPRINTF("Unimplemented Register %x written to\n", offset >> 2);
+ qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
+ HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
/* TODO */
break;
default:
- IPRINTF("%s: Bad offset 0x%x\n", __func__, (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
+ HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
}
}
@@ -284,7 +281,9 @@ static int imx_can_receive(void *opaque)
static void imx_put_data(void *opaque, uint32_t value)
{
IMXSerialState *s = (IMXSerialState *)opaque;
+
DPRINTF("received char\n");
+
s->usr1 |= USR1_RRDY;
s->usr2 |= USR2_RDR;
s->uts1 &= ~UTS1_RXEMPTY;
@@ -319,8 +318,8 @@ static void imx_serial_realize(DeviceState *dev, Error
**errp)
qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive,
imx_event, s);
} else {
- DPRINTF("No char dev for uart at 0x%lx\n",
- (unsigned long)s->iomem.ram_addr);
+ DPRINTF("No char dev for uart at 0x%" HWADDR_PRIx "\n",
+ s->iomem.ram_addr);
}
}
--
1.9.1
- [Qemu-devel] [PULL 20/27] target-arm: Add computation of starting level for S2 PTW, (continued)
- [Qemu-devel] [PULL 20/27] target-arm: Add computation of starting level for S2 PTW, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 01/27] target-arm: Fix "no 64-bit EL2" assumption in arm_excp_unmasked(), Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 07/27] i.MX: Standardize i.MX GPIO debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 10/27] i.MX: Standardize i.MX CCM debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 05/27] hw/arm/virt: don't use a15memmap directly, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 03/27] target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ), Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 04/27] arm_gic_kvm: Disable live migration if not supported, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 15/27] target-arm: lpae: Make t0sz and t1sz signed integers, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 12/27] i.MX: Standardize i.MX EPIT debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 18/27] target-arm: lpae: Replace tsz with computed inputsize, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 06/27] i.MX: Standardize i.MX serial debug.,
Peter Maydell <=
- [Qemu-devel] [PULL 22/27] target-arm: Avoid inline for get_phys_addr, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 08/27] i.MX: Standardize i.MX I2C debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 02/27] target-arm/translate.c: Handle non-executable page-straddling Thumb insns, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 09/27] i.MX: Standardize i.MX AVIC debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 11/27] i.MX: Standardize i.MX FEC debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 27/27] target-arm: Add support for S1 + S2 MMU translations, Peter Maydell, 2015/10/27
- Re: [Qemu-devel] [PULL 00/27] target-arm queue, Peter Maydell, 2015/10/27