[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH for-2.5 v2 4/4] mips: add gic support to malta
From: |
Yongbok Kim |
Subject: |
[Qemu-devel] [PATCH for-2.5 v2 4/4] mips: add gic support to malta |
Date: |
Tue, 27 Oct 2015 17:12:37 +0000 |
Add Global Interrupt Controller support to Malta board.
The I8259 is connected to pin 3 of the GIC.
Increase number of CPUs supported to 32.
Signed-off-by: Yongbok Kim <address@hidden>
---
hw/mips/mips_malta.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 71 insertions(+), 2 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 91c36ba..1e2851e 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -54,6 +54,8 @@
#include "hw/empty_slot.h"
#include "sysemu/kvm.h"
#include "exec/semihost.h"
+#include "hw/misc/mips_gcr.h"
+#include "hw/intc/mips_gic.h"
//#define DEBUG_BOARD_INIT
@@ -92,6 +94,8 @@ typedef struct {
typedef struct {
SysBusDevice parent_obj;
+ MIPSGCRState gcr;
+ MIPSGICState gic;
qemu_irq *i8259;
} MaltaState;
@@ -566,6 +570,52 @@ static MaltaFPGAState *malta_fpga_init(MemoryRegion
*address_space,
return s;
}
+static void gcr_init(MaltaState *s, target_ulong base, Error **err)
+{
+ SysBusDevice *gcrbusdev;
+ DeviceState *gcrdev;
+
+ object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR);
+ qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default());
+
+ gcrdev = DEVICE(&s->gcr);
+
+ object_property_set_int(OBJECT(&s->gcr), smp_cpus, "num-vp", err);
+ object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", err);
+ object_property_set_int(OBJECT(&s->gcr), base, "gcr-base", err);
+ object_property_set_int(OBJECT(&s->gcr), GIC_BASE_ADDR, "gic-base", err);
+ object_property_set_bool(OBJECT(&s->gcr), true, "realized", err);
+ if (*err != NULL) {
+ return;
+ }
+
+ gcrbusdev = SYS_BUS_DEVICE(gcrdev);
+ sysbus_mmio_map(gcrbusdev, 0, base);
+}
+
+static void gic_init(MaltaState *s, Error **err)
+{
+ SysBusDevice *gicbusdev;
+ DeviceState *gicdev;
+ hwaddr gicbase;
+
+ object_initialize(&s->gic, sizeof(s->gic), TYPE_MIPS_GIC);
+ qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
+
+ gicdev = DEVICE(&s->gic);
+ gicbase = object_property_get_int(OBJECT(&s->gcr), "gic-base", err);
+
+ object_property_set_int(OBJECT(&s->gic), smp_cpus, "num-vp", err);
+ object_property_set_int(OBJECT(&s->gic), 128, "num-irq", err);
+ object_property_set_bool(OBJECT(&s->gic), true, "realized", err);
+ if (*err != NULL) {
+ return;
+ }
+
+ gicbusdev = SYS_BUS_DEVICE(gicdev);
+ sysbus_mmio_map(gicbusdev, 0, gicbase);
+}
+
/* Network support */
static void network_init(PCIBus *pci_bus)
{
@@ -1136,6 +1186,21 @@ void mips_malta_init(MachineState *machine)
cpu_mips_irq_init_cpu(env);
cpu_mips_clock_init(env);
+ /* GCR/GIC */
+ if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
+ Error *err = NULL;
+ gcr_init(s, env->CP0_CMGCRBase << 4, &err);
+ if (err != NULL) {
+ error_report("%s", error_get_pretty(err));
+ exit(1);
+ }
+ gic_init(s, &err);
+ if (err != NULL) {
+ error_report("%s", error_get_pretty(err));
+ exit(1);
+ }
+ }
+
/*
* We have a circular dependency problem: pci_bus depends on isa_irq,
* isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
@@ -1155,7 +1220,11 @@ void mips_malta_init(MachineState *machine)
/* Interrupt controller */
/* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
- s->i8259 = i8259_init(isa_bus, env->irq[2]);
+ if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
+ s->i8259 = i8259_init(isa_bus, s->gic.irq_state[3].irq);
+ } else {
+ s->i8259 = i8259_init(isa_bus, env->irq[2]);
+ }
isa_bus_irqs(isa_bus, s->i8259);
pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
@@ -1209,7 +1278,7 @@ static void mips_malta_machine_init(MachineClass *mc)
{
mc->desc = "MIPS Malta Core LV";
mc->init = mips_malta_init;
- mc->max_cpus = 16;
+ mc->max_cpus = 32;
mc->is_default = 1;
}
--
1.7.1