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Re: [Qemu-devel] [PULL 0/9] target-mips queue
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PULL 0/9] target-mips queue |
Date: |
Fri, 30 Oct 2015 17:36:26 +0000 |
On 30 October 2015 at 15:00, Leon Alrae <address@hidden> wrote:
> Hi,
>
> Here's my current target-mips queue, just fixes and relatively minor
> improvements.
>
> Thanks,
> Leon
>
> Cc: Peter Maydell <address@hidden>
> Cc: Aurelien Jarno <address@hidden>
>
> The following changes since commit 7bc8e0c967a4ef77657174d28af775691e18b4ce:
>
> Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
> (2015-10-29 09:49:52 +0000)
>
> are available in the git repository at:
>
> git://github.com/lalrae/qemu.git tags/mips-20151030
>
> for you to fetch changes up to 60270f85cc93d2d34e45b7679c374b1d771f0eeb:
>
> target-mips: fix updating XContext on mmu exception (2015-10-30 14:36:19
> +0000)
>
> ----------------------------------------------------------------
> MIPS patches 2015-10-30
>
> Changes:
> * R6 CPU can be woken up by non-enabled interrupts
> * PC fix in KVM
> * CP0 XContext calculation fix
> * various MIPS R6 updates
Applied, thanks.
-- PMM
- [Qemu-devel] [PULL 0/9] target-mips queue, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 1/9] target-mips: move the test for enabled interrupts to a separate function, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 5/9] hw/mips_malta: Fix KVM PC initialisation, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 9/9] target-mips: fix updating XContext on mmu exception, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 2/9] target-mips: implement the CPU wake-up on non-enabled interrupts in R6, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 6/9] target-mips: add PC, XNP reg numbers to RDHWR, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 3/9] target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 4/9] target-mips: Add enum for BREAK32, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 7/9] target-mips: Set Config5.XNP for R6 cores, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 8/9] target-mips: add SIGRIE instruction, Leon Alrae, 2015/10/30
- Re: [Qemu-devel] [PULL 0/9] target-mips queue,
Peter Maydell <=