Re: [Qemu-devel] [PATCH 09/16] target-arm: Support multiple address spaces in page table walks

[Peter Maydell]

On 9 November 2015 at 11:03, Paolo Bonzini <address@hidden> wrote:
>
>
> On 09/11/2015 11:58, Peter Maydell wrote:
>> You mean "what is the case where is_secure but cpu->num_ases == 1" ?
>> That happens if you have a TrustZone CPU but the board has only
>> connected up one address space, because there is no difference
>> in the view from Secure and NonSecure. (vexpress is like this
>> in hardware, and most of our board models for TZ CPUS are like
>> that now even if the real h/w makes a distinction.)
>>
>> I could have handled that by making the CPU init code always
>> register two ASes (using the same one twice if the board code
>> only passes one or using system_address_space twice if the
>> board code doesn't pass one at all), but that seemed a bit wasteful.
>
> I think it's simpler though.  Complicating the init code is better than
> handling the condition throughout all the helpers...

It was the overhead of having an extra AddressSpace that concerned
me (plus it shows up in things like 'info mtree' somewhat confusingly
if you didn't expect your board to really have 2 ASes). But I don't
feel very strongly about it (or have anything solid to base an
argument either way on).

thanks
-- PMM