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[Qemu-devel] [PATCH 0/3] qemu, pkeys: add memory protection-key support
From: |
Huaitong Han |
Subject: |
[Qemu-devel] [PATCH 0/3] qemu, pkeys: add memory protection-key support |
Date: |
Mon, 9 Nov 2015 19:55:31 +0800 |
The protection-key feature provides an additional mechanism by which IA-32e
paging controls access to usermode addresses.
Hardware support for protection keys for user pages is enumerated with CPUID
feature flag CPUID.7.0.ECX[3]:PKU. Software support is CPUID.7.0.ECX[4]:OSPKE
with the setting of CR4.PKE(bit 22).
The PKRU register is XSAVE-managed state CPUID.D.0.EAX[9], the size of XSAVE
state component for PKRU is 8 bytes, the offset is 0xa80.
The specification of Protection Keys can be found at SDM (4.6.2, volume 3)
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf.
Huaitong Han (3):
qemu, pkeys: add pkeys support for qemu cpuid handling
qemu, pkeys: add pkeys support for qemu xsave state handling
qemu, pkeys: add pkeys support for qemu migration
target-i386/cpu.c | 23 ++++++++++++++++++++++-
target-i386/cpu.h | 7 +++++++
target-i386/kvm.c | 3 +++
target-i386/machine.c | 23 +++++++++++++++++++++++
4 files changed, 55 insertions(+), 1 deletion(-)
--
2.4.3
- [Qemu-devel] [PATCH 0/3] qemu, pkeys: add memory protection-key support,
Huaitong Han <=