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[Qemu-devel] [PULL 2/7] hw/intc/arm_gic: Remove the definition of NUM_CP
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 2/7] hw/intc/arm_gic: Remove the definition of NUM_CPU |
Date: |
Tue, 10 Nov 2015 13:51:42 +0000 |
From: Wei Huang <address@hidden>
arm_gic.c retrieves CPU number using either NUM_CPU(s) or s->num_cpu.
Such mixed-uses make source code inconsistent. This patch removes
NUM_CPU(s), which was defined for MPCore tweak long ago, and instead
favors s->num_cpu. The source is more consistent after this small tweak.
Reviewed-by: Andreas Färber <address@hidden>
Signed-off-by: Wei Huang <address@hidden>
Reviewed-by: Michael Tokarev <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gic.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 8bad132..d71aeb8 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -35,8 +35,6 @@ static const uint8_t gic_id[] = {
0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
};
-#define NUM_CPU(s) ((s)->num_cpu)
-
static inline int gic_get_current_cpu(GICState *s)
{
if (s->num_cpu > 1) {
@@ -64,7 +62,7 @@ void gic_update(GICState *s)
int cpu;
int cm;
- for (cpu = 0; cpu < NUM_CPU(s); cpu++) {
+ for (cpu = 0; cpu < s->num_cpu; cpu++) {
cm = 1 << cpu;
s->current_pending[cpu] = 1023;
if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1))
@@ -567,7 +565,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset,
MemTxAttrs attrs)
if (offset == 4)
/* Interrupt Controller Type Register */
return ((s->num_irq / 32) - 1)
- | ((NUM_CPU(s) - 1) << 5)
+ | ((s->num_cpu - 1) << 5)
| (s->security_extn << 10);
if (offset < 0x08)
return 0;
@@ -1284,7 +1282,7 @@ static void arm_gic_realize(DeviceState *dev, Error
**errp)
* GIC v2 defines a larger memory region (0x1000) so this will need
* to be extended when we implement A15.
*/
- for (i = 0; i < NUM_CPU(s); i++) {
+ for (i = 0; i < s->num_cpu; i++) {
s->backref[i] = s;
memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops,
&s->backref[i], "gic_cpu", 0x100);
--
1.9.1
- [Qemu-devel] [PULL 0/7] target-arm queue, Peter Maydell, 2015/11/10
- [Qemu-devel] [PULL 1/7] target-arm: Fix gdb singlestep handling in arm_debug_excp_handler(), Peter Maydell, 2015/11/10
- [Qemu-devel] [PULL 7/7] target-arm: Clean up DISAS_UPDATE usage in AArch32 translation code, Peter Maydell, 2015/11/10
- [Qemu-devel] [PULL 3/7] arm: boot: Add secure_board_setup flag, Peter Maydell, 2015/11/10
- [Qemu-devel] [PULL 5/7] arm: highbank: Implement PSCI and dummy monitor, Peter Maydell, 2015/11/10
- [Qemu-devel] [PULL 6/7] hw/arm/virt: error_report cleanups, Peter Maydell, 2015/11/10
- [Qemu-devel] [PULL 4/7] arm: highbank: Defeature CPU override, Peter Maydell, 2015/11/10
- [Qemu-devel] [PULL 2/7] hw/intc/arm_gic: Remove the definition of NUM_CPU,
Peter Maydell <=
- Re: [Qemu-devel] [PULL 0/7] target-arm queue, Peter Maydell, 2015/11/10