Re: [Qemu-devel] [Qemu-ppc] [PATCH 13/77] ppc: tlbie, tlbia and tlbisync are HV only

[Benjamin Herrenschmidt]

On Mon, 2015-11-16 at 16:34 +1100, David Gibson wrote:
> On Wed, Nov 11, 2015 at 11:27:26AM +1100, Benjamin Herrenschmidt
> wrote:
> > Not that anything remotely recent supports tlbia but ...
> > 
> > Signed-off-by: Benjamin Herrenschmidt <address@hidden>
> > ---
> >  target-ppc/translate.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> > index 10eb9e3..014fe5e 100644
> > --- a/target-ppc/translate.c
> > +++ b/target-ppc/translate.c
> > @@ -4836,7 +4836,7 @@ static void gen_tlbia(DisasContext *ctx)
> >  #if defined(CONFIG_USER_ONLY)
> >      gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> >  #else
> > -    if (unlikely(ctx->pr)) {
> > +    if (unlikely(ctx->pr || !ctx->hv)) {
> 
> If I'm reading your previous patch correctly, ctx->hv won't be set
> with in problem state, so I think the ctx->pr check is redundant.

Ah you are right. I do have second thoughts about that previous patch
now that you mention it however. In the real MSR, HV and PR are
independant, I wonder if I'm better off making the check explicit...

The reason I did it this way is that afaik, there is no such thing
as a usermode hypervisor resource in the architecture, so any
hypervisor resource is also a supervisor mode one, but having
ctx->hv be 0 when MSR:HV=1 + MSR:PR=1 might make it easy to write
incorrect code in other places when deciding for example how to direct
interrupts.

I'll need to think a bit more about this one.

> >          gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> >          return;
> >      }
> > @@ -4850,7 +4850,7 @@ static void gen_tlbiel(DisasContext *ctx)
> >  #if defined(CONFIG_USER_ONLY)
> >      gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> >  #else
> > -    if (unlikely(ctx->pr)) {
> > +    if (unlikely(ctx->pr || !ctx->hv)) {
> >          gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> >          return;
> >      }
> > @@ -4864,7 +4864,7 @@ static void gen_tlbie(DisasContext *ctx)
> >  #if defined(CONFIG_USER_ONLY)
> >      gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> >  #else
> > -    if (unlikely(ctx->pr)) {
> > +    if (unlikely(ctx->pr || !ctx->hv)) {
> >          gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> >          return;
> >      }
>