Re: [Qemu-devel] [PATCH v2 4/4] target-tilegx: Integrate floating pointer implementation

[Chen Gang]

Excuse me, I copied/pasted the patch to the website, which may generate
the incorrect coding styles.

Please check the attachment in this reply mail for the correct coding
styles (and sorry, the original mail's attachment which I chose is
incorrect).


On 11/17/15 03:43, Chen Gang wrote:
> From d0f0e0a78e81f9589d25b0a2b4ad826d6e55257d Mon Sep 17 00:00:00 2001
> From: Chen Gang <address@hidden>
> Date: Tue, 17 Nov 2015 03:09:18 +0800
> Subject: [PATCH v2 4/4] target-tilegx: Integrate floating pointer 
> implementation
>
> It passes normal building, and gcc testsuite.
>
> Signed-off-by: Chen Gang <address@hidden>
> ---
> target-tilegx/Makefile.objs | 3 +-
> target-tilegx/cpu.h | 2 ++
> target-tilegx/helper.h | 12 ++++++++
> target-tilegx/translate.c | 68 +++++++++++++++++++++++++++++++++++++++------
> 4 files changed, 75 insertions(+), 10 deletions(-)
>
> diff --git a/target-tilegx/Makefile.objs b/target-tilegx/Makefile.objs
> index 0db778f..136ad60 100644
> --- a/target-tilegx/Makefile.objs
> +++ b/target-tilegx/Makefile.objs
> @@ -1 +1,2 @@
> -obj-y += cpu.o translate.o helper.o simd_helper.o
> +obj-y += cpu.o translate.o helper.o simd_helper.o \
> + helper-fsingle.o helper-fdouble.o
> diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
> index 03df107..445a606 100644
> --- a/target-tilegx/cpu.h
> +++ b/target-tilegx/cpu.h
> @@ -88,6 +88,8 @@ typedef struct CPUTLGState {
> uint64_t spregs[TILEGX_SPR_COUNT]; /* Special used registers by outside */
> uint64_t pc; /* Current pc */
>
> + float_status fp_status; /* floating point status */
> +
> #if defined(CONFIG_USER_ONLY)
> uint64_t excaddr; /* exception address */
> uint64_t atomic_srca; /* Arguments to atomic "exceptions" */
> diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
> index 9281d0f..b785bf2 100644
> --- a/target-tilegx/helper.h
> +++ b/target-tilegx/helper.h
> @@ -24,3 +24,15 @@ DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, 
> i64)
> DEF_HELPER_FLAGS_2(v2shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> DEF_HELPER_FLAGS_2(v2shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> DEF_HELPER_FLAGS_2(v2shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> +
> +DEF_HELPER_3(fsingle_add1, i64, env, i64, i64)
> +DEF_HELPER_3(fsingle_sub1, i64, env, i64, i64)
> +DEF_HELPER_3(fsingle_mul1, i64, env, i64, i64)
> +DEF_HELPER_2(fsingle_pack2, i64, env, i64)
> +DEF_HELPER_3(fdouble_unpack_min, i64, env, i64, i64)
> +DEF_HELPER_3(fdouble_unpack_max, i64, env, i64, i64)
> +DEF_HELPER_3(fdouble_add_flags, i64, env, i64, i64)
> +DEF_HELPER_3(fdouble_sub_flags, i64, env, i64, i64)
> +DEF_HELPER_4(fdouble_addsub, i64, env, i64, i64, i64)
> +DEF_HELPER_3(fdouble_mul_flags, i64, env, i64, i64)
> +DEF_HELPER_4(fdouble_pack2, i64, env, i64, i64, i64)
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index b8ca401..4d74b1d 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -597,6 +597,11 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned 
> opext,
> }
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]);
> return ret;
> +
> + case OE_RR_X0(FSINGLE_PACK1):
> + case OE_RR_Y0(FSINGLE_PACK1):
> + mnemonic = "fsingle_pack1";
> + goto done2;
> }
>
> tdest = dest_gr(dc, dest);
> @@ -613,9 +618,6 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned 
> opext,
> gen_helper_cnttz(tdest, tsrca);
> mnemonic = "cnttz";
> break;
> - case OE_RR_X0(FSINGLE_PACK1):
> - case OE_RR_Y0(FSINGLE_PACK1):
> - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> case OE_RR_X1(LD1S):
> memop = MO_SB;
> mnemonic = "ld1s"; /* prefetch_l1_fault */
> @@ -734,6 +736,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned 
> opext,
> return TILEGX_EXCP_OPCODE_UNKNOWN;
> }
>
> +done2:
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
> reg_names[dest], reg_names[srca]);
> return ret;
> @@ -742,13 +745,21 @@ static TileExcp gen_rr_opcode(DisasContext *dc, 
> unsigned opext,
> static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
> unsigned dest, unsigned srca, unsigned srcb)
> {
> - TCGv tdest = dest_gr(dc, dest);
> - TCGv tsrca = load_gr(dc, srca);
> - TCGv tsrcb = load_gr(dc, srcb);
> + TCGv tdest, tsrca, tsrcb;
> TCGv t0;
> const char *mnemonic;
>
> switch (opext) {
> + case OE_RRR(FSINGLE_ADDSUB2, 0, X0):
> + mnemonic = "fsingle_addsub2";
> + goto done2;
> + }
> +
> + tdest = dest_gr(dc, dest);
> + tsrca = load_gr(dc, srca);
> + tsrcb = load_gr(dc, srcb);
> +
> + switch (opext) {
> case OE_RRR(ADDXSC, 0, X0):
> case OE_RRR(ADDXSC, 0, X1):
> gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_add_tl);
> @@ -906,14 +917,39 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, 
> unsigned opext,
> mnemonic = "exch";
> break;
> case OE_RRR(FDOUBLE_ADDSUB, 0, X0):
> + gen_helper_fdouble_addsub(tdest, cpu_env,
> + load_gr(dc, dest),tsrca, tsrcb);
> + mnemonic = "fdouble_addsub";
> + break;
> case OE_RRR(FDOUBLE_ADD_FLAGS, 0, X0):
> + gen_helper_fdouble_add_flags(tdest, cpu_env, tsrca, tsrcb);
> + mnemonic = "fdouble_add_flags";
> + break;
> case OE_RRR(FDOUBLE_MUL_FLAGS, 0, X0):
> + gen_helper_fdouble_mul_flags(tdest, cpu_env, tsrca, tsrcb);
> + mnemonic = "fdouble_mul_flags";
> + break;
> case OE_RRR(FDOUBLE_PACK1, 0, X0):
> + tcg_gen_mov_i64(tdest, tsrcb);
> + mnemonic = "fdouble_pack1";
> + break;
> case OE_RRR(FDOUBLE_PACK2, 0, X0):
> + gen_helper_fdouble_pack2(tdest, cpu_env,
> + load_gr(dc, dest), tsrca, tsrcb);
> + mnemonic = "fdouble_pack2";
> + break;
> case OE_RRR(FDOUBLE_SUB_FLAGS, 0, X0):
> + gen_helper_fdouble_sub_flags(tdest, cpu_env, tsrca, tsrcb);
> + mnemonic = "fdouble_sub_flags";
> + break;
> case OE_RRR(FDOUBLE_UNPACK_MAX, 0, X0):
> + gen_helper_fdouble_unpack_max(tdest, cpu_env, tsrca, tsrcb);
> + mnemonic = "fdouble_unpack_max";
> + break;
> case OE_RRR(FDOUBLE_UNPACK_MIN, 0, X0):
> - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> + gen_helper_fdouble_unpack_min(tdest, cpu_env, tsrca, tsrcb);
> + mnemonic = "fdouble_unpack_min";
> + break;
> case OE_RRR(FETCHADD4, 0, X1):
> gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
> TILEGX_EXCP_OPCODE_FETCHADD4);
> @@ -955,12 +991,25 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, 
> unsigned opext,
> mnemonic = "fetchor";
> break;
> case OE_RRR(FSINGLE_ADD1, 0, X0):
> - case OE_RRR(FSINGLE_ADDSUB2, 0, X0):
> + gen_helper_fsingle_add1(tdest, cpu_env, tsrca, tsrcb);
> + mnemonic = "fsingle_add1";
> + break;
> case OE_RRR(FSINGLE_MUL1, 0, X0):
> + gen_helper_fsingle_mul1(tdest, cpu_env, tsrca, tsrcb);
> + mnemonic = "fsingle_mul1";
> + break;
> case OE_RRR(FSINGLE_MUL2, 0, X0):
> + tcg_gen_mov_i64(tdest, tsrca);
> + mnemonic = "fsingle_mul2";
> + break;
> case OE_RRR(FSINGLE_PACK2, 0, X0):
> + gen_helper_fsingle_pack2(tdest, cpu_env, tsrca);
> + mnemonic = "fsingle_pack2";
> + break;
> case OE_RRR(FSINGLE_SUB1, 0, X0):
> - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> + gen_helper_fsingle_sub1(tdest, cpu_env, tsrca, tsrcb);
> + mnemonic = "fsingle_sub1";
> + break;
> case OE_RRR(MNZ, 0, X0):
> case OE_RRR(MNZ, 0, X1):
> case OE_RRR(MNZ, 4, Y0):
> @@ -1464,6 +1513,7 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, 
> unsigned opext,
> return TILEGX_EXCP_OPCODE_UNKNOWN;
> }
>
> +done2:
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %s", mnemonic,
> reg_names[dest], reg_names[srca], reg_names[srcb]);
> return TILEGX_EXCP_NONE;
> --
> 1.9.3
>
>
>

--
Chen Gang (陈刚)

Open, share, and attitude like air, water, and life which God blessed

v2-0004-target-tilegx-Integrate-floating-pointer-implemen.patch
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