Re: [Qemu-devel] [PATCH] target-arm: Priority masking with basepri on v7m

[Peter Maydell]

On 17 November 2015 at 21:40, François Baldassari
<address@hidden> wrote:
> On armv7m mcus, the BASEPRI register can be set to mask interrupts
> above a certain priority.
>
> This changeset implements that functionality by way of the NVIC which
> ultimately sets the interrupt mask in the GIC.
>
> Signed-off-by: François Baldassari <address@hidden>

There are a lot of problems with our NVIC priority handling
right now. You might like to take a look at the patch set that
Michael Davidsaver sent out earlier this month:
https://lists.nongnu.org/archive/html/qemu-devel/2015-11/msg01542.html

That has some problems but I think it's probably the way we're
going to go to fix up the NVIC.

thanks
-- PMM