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Re: [Qemu-devel] [Qemu-ppc] [PATCH 14/77] ppc: Change 'invalid' bit mask
From: |
David Gibson |
Subject: |
Re: [Qemu-devel] [Qemu-ppc] [PATCH 14/77] ppc: Change 'invalid' bit mask of tlbiel and tlbie |
Date: |
Fri, 20 Nov 2015 18:02:56 +1100 |
User-agent: |
Mutt/1.5.23 (2015-06-09) |
On Wed, Nov 11, 2015 at 11:27:27AM +1100, Benjamin Herrenschmidt wrote:
> Otherwise it will trip on the forms used in recent architecture.
>
> Ideally, we should have different handlers for different architecture
> levels but our current implementation of TLB flushing is dumb enough
> that this will do for now.
>
> Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
> ---
> target-ppc/translate.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 014fe5e..bd5df40 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -9952,8 +9952,10 @@ GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C,
> 0x001F0001, PPC_SEGMENT_64B),
> GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001,
> PPC_SEGMENT_64B),
> #endif
> GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
> -GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
> -GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
> +/* XXX Those instructions will need to be handled differently for
> + * different ISA versions */
> +GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
> +GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
> GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
> #if defined(TARGET_PPC64)
> GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-devel] [PATCH 09/77] ppc: Fix do_rfi() for rfi emulation, (continued)
- [Qemu-devel] [PATCH 08/77] ppc: Add number of threads per core to the processor definition, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-devel] [PATCH 06/77] ppc: Add macros to register hypervisor mode SPRs, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-devel] [PATCH 14/77] ppc: Change 'invalid' bit mask of tlbiel and tlbie, Benjamin Herrenschmidt, 2015/11/10
- Re: [Qemu-devel] [Qemu-ppc] [PATCH 14/77] ppc: Change 'invalid' bit mask of tlbiel and tlbie,
David Gibson <=
- [Qemu-devel] [PATCH 13/77] ppc: tlbie, tlbia and tlbisync are HV only, Benjamin Herrenschmidt, 2015/11/10
[Qemu-devel] [PATCH 19/77] ppc: Fix POWER7 and POWER8 exception definitions, Benjamin Herrenschmidt, 2015/11/10
[Qemu-devel] [PATCH 17/77] ppc: Add PPC_64H instruction flag to POWER7 and POWER8, Benjamin Herrenschmidt, 2015/11/10
[Qemu-devel] [PATCH 20/77] ppc: Fix generation if ISI/DSI vs. HV mode, Benjamin Herrenschmidt, 2015/11/10