Re: [Qemu-devel] [PATCH] PCI: minor performance optimization

[Cao jin]

On 11/20/2015 09:30 PM, Michael S. Tsirkin wrote:
> On Fri, Nov 20, 2015 at 07:58:01PM +0800, Cao jin wrote:
> > On 11/20/2015 07:26 PM, Michael S. Tsirkin wrote:
> > > On Fri, Nov 20, 2015 at 07:04:07PM +0800, Cao jin wrote:
> > > > On 11/20/2015 06:45 PM, Michael S. Tsirkin wrote:
> > > > > On Fri, Nov 20, 2015 at 06:45:01PM +0800, Cao jin wrote:
> > > > >
> > > > > > 2. As spec says, each capability must be DWORD aligned, so an optimization can
> > > > > >     be done via Loop Unrolling.
> > > > >
> > > > > Why do we want to optimize it?
> > > >
> > > > For tiny performance improvement via less loop. take pcie express
> > > > capability(60 bytes at most) for example, it may loop 60 times, now we just
> > > > need 15 times, a quarter of before.
> > >
> > > But who cares? This is not a data path operation.
> >
> > It is tiny thing I found when browsing code. When found there are several
> > places looks like this, I think maybe it does good to qemu to do this and
> > CCed to you because it don`t look like a simple trivial patch.
> >
> > So, hey Michael, if you don`t like this kind of optimization, that`t ok,
> > forget it. But I think it make me little confused when determine which kind
> > of patch should be CCed to you.
>
> Optimization patches should normally include performance numbers
> if they are to be merged.
> Try to come up with a benchmark and you will realize that the speed of
> this function has no effect under even half way realistic conditions.

Maybe you are right. OK, will send the param check patch to the qemu-trivial

> > > > > .
> > > >
> > > > --
> > > > Yours Sincerely,
> > > >
> > > > Cao Jin
> > > .
> >
> > --
> > Yours Sincerely,
> >
> > Cao Jin
> .

--
Yours Sincerely,

Cao Jin