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[Qemu-devel] [PATCH v2 26/26] armv7m: decide whether faults are MemManag
From: |
Michael Davidsaver |
Subject: |
[Qemu-devel] [PATCH v2 26/26] armv7m: decide whether faults are MemManage or BusFault |
Date: |
Wed, 2 Dec 2015 19:18:53 -0500 |
General logic is that operations stopped by the MPU are MemManage,
and those which go through the MPU and are caught by the unassigned
handle are BusFault.
---
target-arm/helper.c | 35 +++++++++++++++++++++++++++++------
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c890b3a..630d5c9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5546,12 +5546,35 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
break;
case EXCP_PREFETCH_ABORT:
case EXCP_DATA_ABORT:
- /* TODO: if we implemented the MPU registers, this is where we
- * should set the MMFAR, etc from exception.fsr and exception.vaddress.
- */
- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
- env->v7m.mmfar = env->exception.vaddress;
- env->v7m.cfsr = (1<<1)|(1<<7); /* DACCVIOL and MMARVALID */
+ switch (env->exception.fsr & 0xf) {
+ case 0x8: /* External Abort */
+ switch (cs->exception_index) {
+ case EXCP_PREFETCH_ABORT:
+ env->v7m.cfsr |= (1<<(8+1)); /* PRECISERR */
+ break;
+ case EXCP_DATA_ABORT:
+ env->v7m.cfsr |= (1<<(8+0)); /* IBUSERR */
+ break;
+ }
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS);
+ env->v7m.bfar = env->exception.vaddress;
+ env->v7m.cfsr |= (1<<(8+7)); /* BFARVALID */
+ break;
+ case 0xd: /* Permission fault */
+ default:
+ switch (cs->exception_index) {
+ case EXCP_PREFETCH_ABORT:
+ env->v7m.cfsr |= (1<<0); /* IACCVIOL */
+ break;
+ case EXCP_DATA_ABORT:
+ env->v7m.cfsr |= (1<<1); /* DACCVIOL */
+ break;
+ }
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
+ env->v7m.mmfar = env->exception.vaddress;
+ env->v7m.cfsr |= (1<<7); /* MMARVALID */
+ break;
+ }
break;
case EXCP_BKPT:
if (semihosting_enabled()) {
--
2.1.4
- [Qemu-devel] [PATCH v2 14/26] armv7m: prevent unprivileged write to STIR, (continued)
- [Qemu-devel] [PATCH v2 14/26] armv7m: prevent unprivileged write to STIR, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 13/26] armv7m: implement CCR, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 18/26] armv7m: update base region policy, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 17/26] armv7m: mpu background miss is perm fault, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 23/26] qom: add cpu_generic_init_unrealized(), Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 25/26] armv7m: remove extra cpu_reset(), Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 24/26] armv7m: split armv7m_init in two parts, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 21/26] armv7m: CONTROL<1> handling, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 26/26] armv7m: decide whether faults are MemManage or BusFault,
Michael Davidsaver <=
- [Qemu-devel] [PATCH v2 08/26] armv7m: rewrite NVIC, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 19/26] armv7m: mpu not allowed to map exception return codes, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 20/26] armv7m: observable initial register state, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 16/26] armv7m: add some mpu debugging prints, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 15/26] armv7m: add MPU to cortex-m3 and cortex-m4, Michael Davidsaver, 2015/12/02
- [Qemu-devel] [PATCH v2 22/26] armv7m: priority field mask, Michael Davidsaver, 2015/12/02
- Re: [Qemu-devel] [PATCH v2 00/26] armv7m: exception handling, MPU, and more, Peter Maydell, 2015/12/17