[Qemu-devel] [RFC v6 08/14] target-arm: Add atomic_clear helper for CLREX insn

[Alvise Rigo]

Add a simple helper function to emulate the CLREX instruction.

Suggested-by: Jani Kokkonen <address@hidden>
Suggested-by: Claudio Fontana <address@hidden>
Signed-off-by: Alvise Rigo <address@hidden>
---
 target-arm/helper.h    | 2 ++
 target-arm/op_helper.c | 6 ++++++
 target-arm/translate.c | 1 +
 3 files changed, 9 insertions(+)

diff --git a/target-arm/helper.h b/target-arm/helper.h
index c2a85c7..37cec49 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -532,6 +532,8 @@ DEF_HELPER_2(dc_zva, void, env, i64)
 DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64)
 
+DEF_HELPER_1(atomic_clear, void, env)
+
 #ifdef TARGET_AARCH64
 #include "helper-a64.h"
 #endif
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 6cd54c8..5a67557 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -50,6 +50,12 @@ static int exception_target_el(CPUARMState *env)
     return target_el;
 }
 
+void HELPER(atomic_clear)(CPUARMState *env)
+{
+    ENV_GET_CPU(env)->excl_protected_range.begin = -1;
+    ENV_GET_CPU(env)->ll_sc_context = false;
+}
+
 uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
                           uint32_t rn, uint32_t maxindex)
 {
diff --git a/target-arm/translate.c b/target-arm/translate.c
index e88d8a3..e0362e0 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -7514,6 +7514,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, 
int rt2,
 static void gen_clrex(DisasContext *s)
 {
 #ifdef CONFIG_TCG_USE_LDST_EXCL
+    gen_helper_atomic_clear(cpu_env);
 #else
     tcg_gen_movi_i64(cpu_exclusive_addr, -1);
 #endif
-- 
2.6.4