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[Qemu-devel] [PATCH v2 38/51] pc: acpi: q35: move GSI links to SSDT
From: |
Igor Mammedov |
Subject: |
[Qemu-devel] [PATCH v2 38/51] pc: acpi: q35: move GSI links to SSDT |
Date: |
Mon, 28 Dec 2015 18:02:45 +0100 |
Signed-off-by: Igor Mammedov <address@hidden>
---
hw/i386/acpi-build.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
hw/i386/q35-acpi-dsdt.dsl | 34 ++++++++--------------------------
2 files changed, 55 insertions(+), 26 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index df5e835..4edd989 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1498,6 +1498,31 @@ static Aml *build_link_dev(const char *name, uint8_t
uid, Aml *reg)
return dev;
}
+static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
+{
+ Aml *dev;
+ Aml *crs;
+ Aml *method;
+ uint32_t irqs;
+
+ dev = aml_device("%s", name);
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
+
+ crs = aml_resource_template();
+ irqs = gsi;
+ aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_SHARED, &irqs, 1));
+ aml_append(dev, aml_name_decl("_PRS", crs));
+
+ aml_append(dev, aml_name_decl("_CRS", crs));
+
+ method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
+ aml_append(dev, method);
+
+ return dev;
+}
+
static void build_piix4_pci0_int(Aml *table)
{
Aml *dev;
@@ -1588,6 +1613,26 @@ static void build_piix4_pci0_int(Aml *table)
aml_append(table, sb_scope);
}
+static void build_q35_pci0_int(Aml *table)
+{
+ Aml *sb_scope = aml_scope("_SB");
+
+ /*
+ * TODO: UID probably shouldn't be the same for GSIx devices
+ * but that's how it was in original ASL so keep it for now
+ */
+ aml_append(sb_scope, build_gsi_link_dev("GSIA", 0, 0x10));
+ aml_append(sb_scope, build_gsi_link_dev("GSIB", 0, 0x11));
+ aml_append(sb_scope, build_gsi_link_dev("GSIC", 0, 0x12));
+ aml_append(sb_scope, build_gsi_link_dev("GSID", 0, 0x13));
+ aml_append(sb_scope, build_gsi_link_dev("GSIE", 0, 0x14));
+ aml_append(sb_scope, build_gsi_link_dev("GSIF", 0, 0x15));
+ aml_append(sb_scope, build_gsi_link_dev("GSIG", 0, 0x16));
+ aml_append(sb_scope, build_gsi_link_dev("GSIH", 0, 0x17));
+
+ aml_append(table, sb_scope);
+}
+
static void build_piix4_pm(Aml *table)
{
Aml *dev;
@@ -1716,7 +1761,9 @@ build_ssdt(GArray *table_data, GArray *linker,
} else {
build_hpet_aml(ssdt);
build_isa_devices_aml(ssdt);
+ build_q35_pci0_int(ssdt);
}
+
build_cpu_hotplug_aml(ssdt);
build_memory_hotplug_aml(ssdt, nr_mem, pm->mem_hp_io_base,
pm->mem_hp_io_len);
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index e157615..f2c154a 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -348,31 +348,13 @@ DefinitionBlock (
define_link(LNKG, 6, PRQG)
define_link(LNKH, 7, PRQH)
-#define define_gsi_link(link, uid, gsi) \
- Device(link) { \
- Name(_HID, EISAID("PNP0C0F")) \
- Name(_UID, uid) \
- Name(_PRS, ResourceTemplate() { \
- Interrupt(, Level, ActiveHigh, Shared) { \
- gsi \
- } \
- }) \
- Name(_CRS, ResourceTemplate() { \
- Interrupt(, Level, ActiveHigh, Shared) { \
- gsi \
- } \
- }) \
- Method(_SRS, 1, NotSerialized) { \
- } \
- }
-
- define_gsi_link(GSIA, 0, 0x10)
- define_gsi_link(GSIB, 0, 0x11)
- define_gsi_link(GSIC, 0, 0x12)
- define_gsi_link(GSID, 0, 0x13)
- define_gsi_link(GSIE, 0, 0x14)
- define_gsi_link(GSIF, 0, 0x15)
- define_gsi_link(GSIG, 0, 0x16)
- define_gsi_link(GSIH, 0, 0x17)
+ External(GSIA, DeviceObj)
+ External(GSIB, DeviceObj)
+ External(GSIC, DeviceObj)
+ External(GSID, DeviceObj)
+ External(GSIE, DeviceObj)
+ External(GSIF, DeviceObj)
+ External(GSIG, DeviceObj)
+ External(GSIH, DeviceObj)
}
}
--
1.8.3.1
- [Qemu-devel] [PATCH v2 37/51] pc: acpi: piix4: acpi move PCI0 device to SSDT, (continued)
- [Qemu-devel] [PATCH v2 37/51] pc: acpi: piix4: acpi move PCI0 device to SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 34/51] pc: acpi: piix4: move IQST() into SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 30/51] pc: acpi: move PIIX4 isa-bridge and pm devices into SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 31/51] pc: acpi: move remaining GPE handlers into SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 32/51] pc: acpi: pci: move link devices into SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 33/51] pc: acpi: piix4: move IQCR() into SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 40/51] pc: acpi: q35: move IQCR() into SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 42/51] pc: acpi: q35: move ISA bridge into SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 45/51] pc: acpi: q35: move PRTP routing table into SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 35/51] pc: acpi: piix4: move PCI0._PRT() into SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 38/51] pc: acpi: q35: move GSI links to SSDT,
Igor Mammedov <=
- [Qemu-devel] [PATCH v2 39/51] pc: acpi: q35: move link devices to SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 41/51] pc: acpi: q35: move IQST() into SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 43/51] pc: acpi: q35: move _PRT() into SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 44/51] pc: acpi: q35: move PRTA routing table into SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 46/51] pc: acpi: q35: move _PIC() method into SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 47/51] pc: acpi: q35: move PCI0._OSC() method into SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 48/51] pc: acpi: q35: move PCI0 device definition into SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 49/51] pc: acpi: q35: PCST, PCSB opregions and PCIB field into SSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 50/51] pc: acpi: switch to AML API composed DSDT, Igor Mammedov, 2015/12/28
- [Qemu-devel] [PATCH v2 51/51] pc: acpi: remove unused ASL templates and related blobs/utils, Igor Mammedov, 2015/12/28