Re: [Qemu-devel] [PATCH] sdhci: add quirk property for card insert interrupt status on Raspberry Pi

[Peter Crosthwaite]

On Mon, Jan 4, 2016 at 2:12 PM, Andrew Baumann
<address@hidden> wrote:
>> From: Peter Crosthwaite [mailto:address@hidden
>> Sent: Thursday, 31 December 2015 21:38
>> On Thu, Dec 31, 2015 at 1:40 PM, Andrew Baumann
>> <address@hidden> wrote:
>> > This quirk is a workaround for the following hardware behaviour, on
>> > which UEFI (specifically, the bootloader for Windows on Pi2) depends:
>> >
>> > 1. at boot with an SD card present, the interrupt status/enable
>> >    registers are initially zero
>> > 2. upon enabling it in the interrupt enable register, the card insert
>> >    bit in the interrupt status register is immediately set
>> > 3. after a subsequent controller reset, the card insert interrupt does
>> >    not fire, even if enabled in the interrupt enable register
>> >
>>
>> This is a baffling symptom. Does prnsts card ejection state fully work
>> with physical card ejections and insertions both before and after the
>> subsequent controller reset?
>
> I just tested this, by polling prnsts and intsts in a tight loop at board 
> startup. At power on with a card inserted, prnsts reads 1FFF0000. Subsequent 
> removal of the card, re-insertion etc. does not change its value.

Does either the subsequent reset or the interrupt ack change it? I'm
assuming it is stuck permanently at 1fff.

>After enabling interrupts, I reliably see a card insert interrupt in intsts. 
>If I then write zero to the interrupt enable register, the pending card insert 
>interrupt remains, which seems to dispel the "mask on read" theory. Once acked 
>or reset, the card insert interrupt never recurs. I never saw a card removal 
>interrupt.
>

So

* interrupt status is initially 0
* writing one to enable triggers the ghost
* it can only be cleared with a status ack
* you can never get a second ghost

This means you have two latches as there is no way it can be driven by
the raw pin, state, otherwise it would recur.

> I did once see a card interrupt (0x100, i.e. the one that comes from the card 
> itself, not the controller) after re-inserting the card, but I think that's 
> irrelevant.
>
> It's impossible to boot the Pi without having a card inserted (well, maybe 
> with a jtag debugger), but I did try inserting the card around 0.5s after 
> applying power, and the results were the same.
>
> So, without the prnsts bits, I can't confirm or deny your theory about 
> debouncing logic,

It's disproven if you can never observe something other than 1FFF0000
for prnsts anyway.

> but either way there is a reliable ghost of a card insertion interrupt that 
> is signalled at power on, and remains pending until it is either acked or the 
> controller reset, after which point it never recurs. And I'd really like to 
> model that somehow without making a mess of sdhci.c :) Any ideas?
>

Ok, I think it can be explained as a bad top-level connection as
follows. The pin is mis-connected in such a way that such that it sees
one edge on the POR reset and never sees any action again. The
controller considers this pin edge-triggered and has the penning quirk
as well, that is it saves edge interrupt until they are enabled and
then releases them singly to the status register.

This doesn't explain why the controller doesn't see the interrupt on
the soft reset, but perhaps that is explained by the spec, as I don't
see anywhere that says that the interrupt has to retrigger for a
constantly inserted card over a controller reset. Might be
implementation specific.

Looking at the set_cb stuff, I think the guard on your original quirk
implementation may be missing for the sd_set_cb() in sdhci_initfn().
If this guard were added that quirk would be more complete, as
currently it probably is seeing action on changes of state.

I think the way to correct the original quirk is to:

* make both sd_set_cb()'s conditional
* manually call insert_eject_cb() on the POR reset (call the CB
instead of register it).

Note that sdhci has no device::reset callback. You could add this to
implement your POR reset.

You then have the problem of the prnsts register, which I assume it
getting blasted by the reset memset. That can be managed by
specifically preserving those two bits of prnsts through the reset
(with an accompanying comment that this is needed for your quirk).

Your patch as-is here doesn't seem to address the penning behaviour
(where the interrupt status remains clear until it is enabled), maybe
that can be added as a second quirk if needed later?

Regards,
Peter

> Andrew