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[Qemu-devel] [PULL v2 39/59] pc: acpi: piix4: move remaining PCI hotplug
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL v2 39/59] pc: acpi: piix4: move remaining PCI hotplug bits into SSDT |
Date: |
Sat, 9 Jan 2016 23:41:16 +0200 |
From: Igor Mammedov <address@hidden>
Signed-off-by: Igor Mammedov <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
hw/i386/acpi-build.c | 43 +++++++++++++++++++++++++++++++++++++++++++
hw/i386/acpi-dsdt.dsl | 40 ----------------------------------------
2 files changed, 43 insertions(+), 40 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 5dd25e1..f929bb8 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1637,6 +1637,48 @@ static void build_piix4_isa_bridge(Aml *table)
aml_append(table, scope);
}
+static void build_piix4_pci_hotplug(Aml *table)
+{
+ Aml *scope;
+ Aml *field;
+ Aml *method;
+
+ scope = aml_scope("_SB.PCI0");
+
+ aml_append(scope,
+ aml_operation_region("PCST", AML_SYSTEM_IO, 0xae00, 0x08));
+ field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
+ aml_append(field, aml_named_field("PCIU", 32));
+ aml_append(field, aml_named_field("PCID", 32));
+ aml_append(scope, field);
+
+ aml_append(scope,
+ aml_operation_region("SEJ", AML_SYSTEM_IO, 0xae08, 0x04));
+ field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
+ aml_append(field, aml_named_field("B0EJ", 32));
+ aml_append(scope, field);
+
+ aml_append(scope,
+ aml_operation_region("BNMR", AML_SYSTEM_IO, 0xae10, 0x04));
+ field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
+ aml_append(field, aml_named_field("BNUM", 32));
+ aml_append(scope, field);
+
+ aml_append(scope, aml_mutex("BLCK", 0));
+
+ method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
+ aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
+ aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
+ aml_append(method,
+ aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
+ aml_append(method, aml_release(aml_name("BLCK")));
+ aml_append(method, aml_return(aml_int(0)));
+ aml_append(scope, method);
+
+ aml_append(table, scope);
+}
+
+
static void
build_ssdt(GArray *table_data, GArray *linker,
AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
@@ -1663,6 +1705,7 @@ build_ssdt(GArray *table_data, GArray *linker,
build_piix4_pm(ssdt);
build_piix4_isa_bridge(ssdt);
build_isa_devices_aml(ssdt);
+ build_piix4_pci_hotplug(ssdt);
build_piix4_pci0_int(ssdt);
} else {
build_hpet_aml(ssdt);
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
index 5d741dd..a7769fc 100644
--- a/hw/i386/acpi-dsdt.dsl
+++ b/hw/i386/acpi-dsdt.dsl
@@ -38,44 +38,4 @@ DefinitionBlock (
// External(PX13, DeviceObj)
}
}
-
-/****************************************************************
- * PCI hotplug
- ****************************************************************/
-
- Scope(\_SB.PCI0) {
- OperationRegion(PCST, SystemIO, 0xae00, 0x08)
- Field(PCST, DWordAcc, NoLock, WriteAsZeros) {
- PCIU, 32,
- PCID, 32,
- }
-
- OperationRegion(SEJ, SystemIO, 0xae08, 0x04)
- Field(SEJ, DWordAcc, NoLock, WriteAsZeros) {
- B0EJ, 32,
- }
-
- OperationRegion(BNMR, SystemIO, 0xae10, 0x04)
- Field(BNMR, DWordAcc, NoLock, WriteAsZeros) {
- BNUM, 32,
- }
-
- /* Lock to protect access to fields above. */
- Mutex(BLCK, 0)
-
- /* Methods called by bulk generated PCI devices below */
-
- /* Methods called by hotplug devices */
- Method(PCEJ, 2, NotSerialized) {
- // _EJ0 method - eject callback
- Acquire(BLCK, 0xFFFF)
- Store(Arg0, BNUM)
- Store(ShiftLeft(1, Arg1), B0EJ)
- Release(BLCK)
- Return (0x0)
- }
-
- /* Hotplug notification method supplied by SSDT */
- External(\_SB.PCI0.PCNT, MethodObj)
- }
}
--
MST
- [Qemu-devel] [PULL v2 29/59] pc: acpi: move MOU device from DSDT to SSDT, (continued)
- [Qemu-devel] [PULL v2 29/59] pc: acpi: move MOU device from DSDT to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 30/59] pc: acpi: move FDC0 device from DSDT to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 31/59] pc: acpi: move LPT device from DSDT to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 32/59] pc: acpi: move COM devices from DSDT to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 33/59] pc: acpi: move PIIX4 isa-bridge and pm devices into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 34/59] pc: acpi: move remaining GPE handlers into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 35/59] pc: acpi: pci: move link devices into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 36/59] pc: acpi: piix4: move IQCR() into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 37/59] pc: acpi: piix4: move IQST() into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 38/59] pc: acpi: piix4: move PCI0._PRT() into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 39/59] pc: acpi: piix4: move remaining PCI hotplug bits into SSDT,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL v2 40/59] pc: acpi: piix4: acpi move PCI0 device to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 41/59] pc: acpi: q35: move GSI links to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 42/59] pc: acpi: q35: move link devices to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 43/59] pc: acpi: q35: move IQCR() into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 44/59] pc: acpi: q35: move IQST() into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 46/59] pc: acpi: q35: move _PRT() into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 45/59] pc: acpi: q35: move ISA bridge into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 47/59] pc: acpi: q35: move PRTA routing table into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 49/59] pc: acpi: q35: move _PIC() method into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 48/59] pc: acpi: q35: move PRTP routing table into SSDT, Michael S. Tsirkin, 2016/01/09