[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 00/36] target-arm queue
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 00/36] target-arm queue |
Date: |
Thu, 21 Jan 2016 14:55:53 +0000 |
The biggie here is the multi-ases support and corresponding TrustZone
support code. There are also a bunch of other comparatively minor
things...
thanks
-- PMM
The following changes since commit 3c9331c47f22224118d5019b0af8eac704824d8d:
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
(2016-01-21 13:09:47 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20160121
for you to fetch changes up to 03fbf20f4da58f41998dc10ec7542f65d37ba759:
target-arm: Implement FPEXC32_EL2 system register (2016-01-21 14:15:09 +0000)
----------------------------------------------------------------
target-arm queue:
* connect SPI devices in Xilinx Zynq platforms
* multiple-address-space support
* use multiple-address-space support for ARM TrustZone
* arm_gic: return correct ID registers for 11MPCore/v1/v2 GICs
* various fixes for (currently disabled) AArch64 EL2 and EL3 support
* add 'always-on' property to the virt board timer DT entry
----------------------------------------------------------------
Alistair Francis (6):
m25p80.c: Add sst25wf080 SPI flash device
ssi: Move ssi.h into a separate directory
xilinx_spips: Separate the state struct into a header
xlnx-zynqmp: Connect the SPI devices
xlnx-ep108: Connect the SPI Flash
arm_gic: Update ID registers based on revision
Christoffer Dall (1):
hw/arm/virt: Add always-on property to the virt board timer
Peter Crosthwaite (4):
qdev: get_child_bus(): Use QOM lookup if available
misc: zynq-xadc: Fix off-by-one
memory: Add address_space_init_shareable()
qom/cpu: Add MemoryRegion property
Peter Maydell (25):
exec.c: Don't set cpu->as until cpu_address_space_init
exec.c: Allow target CPUs to define multiple AddressSpaces
exec-all.h: Document tlb_set_page_with_attrs, tlb_set_page
cpu: Add new get_phys_page_attrs_debug() method
cpu: Add new asidx_from_attrs() method
cputlb.c: Use correct address space when looking up MemoryRegionSection
exec.c: Pass MemTxAttrs to iotlb_to_region so it uses the right AS
exec.c: Add cpu_get_address_space()
exec.c: Use cpu_get_phys_page_attrs_debug
exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_write
target-arm: Add QOM property for Secure memory region
target-arm: Implement asidx_from_attrs
target-arm: Implement cpu_get_phys_page_attrs_debug
target-arm: Support multiple address spaces in page table walks
hw/arm/virt: Wire up memory region to CPUs explicitly
hw/arm/virt: add secure memory region and UART
target-arm: Properly support EL2 and EL3 in arm_el_is_aa64()
target-arm: Move aarch64_cpu_do_interrupt() to helper.c
target-arm: Use a single entry point for AArch64 and AArch32 exceptions
target-arm: Pull semihosting handling out to arm_cpu_do_interrupt()
target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target
target-arm: Handle exception return from AArch64 to non-EL0 AArch32
target-arm: Implement remaining illegal return event checks
target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode
target-arm: Implement FPEXC32_EL2 system register
cpus.c | 13 +-
cputlb.c | 9 +-
exec.c | 103 ++++++++----
hw/arm/pxa2xx.c | 2 +-
hw/arm/spitz.c | 2 +-
hw/arm/stellaris.c | 2 +-
hw/arm/strongarm.c | 2 +-
hw/arm/tosa.c | 2 +-
hw/arm/virt.c | 59 ++++++-
hw/arm/xilinx_zynq.c | 2 +-
hw/arm/xlnx-ep108.c | 16 ++
hw/arm/xlnx-zynqmp.c | 31 ++++
hw/arm/z2.c | 2 +-
hw/block/m25p80.c | 3 +-
hw/core/qdev.c | 6 +
hw/display/ads7846.c | 2 +-
hw/display/ssd0323.c | 2 +-
hw/intc/arm_gic.c | 35 ++++-
hw/microblaze/petalogix_ml605_mmu.c | 2 +-
hw/misc/max111x.c | 2 +-
hw/misc/zynq-xadc.c | 2 +-
hw/sd/ssi-sd.c | 2 +-
hw/ssi/pl022.c | 2 +-
hw/ssi/ssi.c | 2 +-
hw/ssi/xilinx_spi.c | 2 +-
hw/ssi/xilinx_spips.c | 48 +-----
include/exec/exec-all.h | 69 ++++++++-
include/exec/memory.h | 18 +++
include/hw/arm/virt.h | 1 +
include/hw/arm/xlnx-zynqmp.h | 3 +
include/hw/{ => ssi}/ssi.h | 10 +-
include/hw/ssi/xilinx_spips.h | 72 +++++++++
include/qom/cpu.h | 57 ++++++-
memory.c | 27 ++++
softmmu_template.h | 4 +-
target-arm/cpu-qom.h | 8 +-
target-arm/cpu.c | 35 ++++-
target-arm/cpu.h | 56 +++++--
target-arm/cpu64.c | 3 -
target-arm/helper-a64.c | 104 -------------
target-arm/helper.c | 301 +++++++++++++++++++++++++++++-------
target-arm/op_helper.c | 94 ++++++++---
target-i386/cpu.c | 7 +-
43 files changed, 909 insertions(+), 315 deletions(-)
rename include/hw/{ => ssi}/ssi.h (96%)
create mode 100644 include/hw/ssi/xilinx_spips.h
- [Qemu-devel] [PULL 00/36] target-arm queue,
Peter Maydell <=
- [Qemu-devel] [PULL 35/36] target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 33/36] target-arm: Handle exception return from AArch64 to non-EL0 AArch32, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 32/36] target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 31/36] target-arm: Pull semihosting handling out to arm_cpu_do_interrupt(), Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 28/36] target-arm: Properly support EL2 and EL3 in arm_el_is_aa64(), Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 20/36] target-arm: Add QOM property for Secure memory region, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 27/36] arm_gic: Update ID registers based on revision, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 23/36] target-arm: Support multiple address spaces in page table walks, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 29/36] target-arm: Move aarch64_cpu_do_interrupt() to helper.c, Peter Maydell, 2016/01/21
- [Qemu-devel] [PULL 26/36] hw/arm/virt: Add always-on property to the virt board timer, Peter Maydell, 2016/01/21