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[Qemu-devel] [PULL 39/39] target-ppc: Make every FPSCR_ macro have a cor
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 39/39] target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro |
Date: |
Fri, 29 Jan 2016 16:07:11 +1100 |
From: James Clarke <address@hidden>
Signed-off-by: James Clarke <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/cpu.h | 31 ++++++++++++++++++++++---------
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 0820390..f300c86 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -687,24 +687,37 @@ enum {
#define FP_FX (1ull << FPSCR_FX)
#define FP_FEX (1ull << FPSCR_FEX)
+#define FP_VX (1ull << FPSCR_VX)
#define FP_OX (1ull << FPSCR_OX)
-#define FP_OE (1ull << FPSCR_OE)
#define FP_UX (1ull << FPSCR_UX)
-#define FP_UE (1ull << FPSCR_UE)
-#define FP_XX (1ull << FPSCR_XX)
-#define FP_XE (1ull << FPSCR_XE)
#define FP_ZX (1ull << FPSCR_ZX)
-#define FP_ZE (1ull << FPSCR_ZE)
-#define FP_VX (1ull << FPSCR_VX)
+#define FP_XX (1ull << FPSCR_XX)
#define FP_VXSNAN (1ull << FPSCR_VXSNAN)
#define FP_VXISI (1ull << FPSCR_VXISI)
-#define FP_VXIMZ (1ull << FPSCR_VXIMZ)
-#define FP_VXZDZ (1ull << FPSCR_VXZDZ)
#define FP_VXIDI (1ull << FPSCR_VXIDI)
+#define FP_VXZDZ (1ull << FPSCR_VXZDZ)
+#define FP_VXIMZ (1ull << FPSCR_VXIMZ)
#define FP_VXVC (1ull << FPSCR_VXVC)
+#define FP_FR (1ull << FSPCR_FR)
+#define FP_FI (1ull << FPSCR_FI)
+#define FP_C (1ull << FPSCR_C)
+#define FP_FL (1ull << FPSCR_FL)
+#define FP_FG (1ull << FPSCR_FG)
+#define FP_FE (1ull << FPSCR_FE)
+#define FP_FU (1ull << FPSCR_FU)
+#define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
+#define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU)
+#define FP_VXSOFT (1ull << FPSCR_VXSOFT)
+#define FP_VXSQRT (1ull << FPSCR_VXSQRT)
#define FP_VXCVI (1ull << FPSCR_VXCVI)
#define FP_VE (1ull << FPSCR_VE)
-#define FP_FI (1ull << FPSCR_FI)
+#define FP_OE (1ull << FPSCR_OE)
+#define FP_UE (1ull << FPSCR_UE)
+#define FP_ZE (1ull << FPSCR_ZE)
+#define FP_XE (1ull << FPSCR_XE)
+#define FP_NI (1ull << FPSCR_NI)
+#define FP_RN1 (1ull << FPSCR_RN1)
+#define FP_RN (1ull << FPSCR_RN)
/*****************************************************************************/
/* Vector status and control register */
--
2.5.0
- [Qemu-devel] [PULL 21/39] target-ppc: gdbstub: fix float registers for little-endian guests, (continued)
- [Qemu-devel] [PULL 21/39] target-ppc: gdbstub: fix float registers for little-endian guests, David Gibson, 2016/01/29
- [Qemu-devel] [PULL 18/39] pseries: Clean up error reporting in htab migration functions, David Gibson, 2016/01/29
- [Qemu-devel] [PULL 24/39] target-ppc: gdbstub: fix spe registers for little-endian guests, David Gibson, 2016/01/29
- [Qemu-devel] [PULL 35/39] target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one(), David Gibson, 2016/01/29
- [Qemu-devel] [PULL 38/39] target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG, David Gibson, 2016/01/29
- [Qemu-devel] [PULL 37/39] target-ppc: Helper to determine page size information from hpte alone, David Gibson, 2016/01/29
- [Qemu-devel] [PULL 03/39] macio: use the existing IDEDMA aiocb to hold the active DMA aiocb, David Gibson, 2016/01/29
- [Qemu-devel] [PULL 32/39] target-ppc: Rework SLB page size lookup, David Gibson, 2016/01/29
- [Qemu-devel] [PULL 39/39] target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro,
David Gibson <=
- [Qemu-devel] [PULL 36/39] target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs, David Gibson, 2016/01/29
- [Qemu-devel] [PULL 02/39] target-ppc: use cpu_write_xer() helper in cpu_post_load, David Gibson, 2016/01/29
- [Qemu-devel] [PULL 31/39] target-ppc: Rework ppc_store_slb, David Gibson, 2016/01/29
- [Qemu-devel] [PULL 30/39] target-ppc: Convert mmu-hash{32, 64}.[ch] from CPUPPCState to PowerPCCPU, David Gibson, 2016/01/29