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[Qemu-devel] [RFC v7 03/16] softmmu: Simplify helper_*_st_name, wrap MM
From: |
Alvise Rigo |
Subject: |
[Qemu-devel] [RFC v7 03/16] softmmu: Simplify helper_*_st_name, wrap MMIO code |
Date: |
Fri, 29 Jan 2016 10:32:32 +0100 |
Attempting to simplify the helper_*_st_name, wrap the MMIO code into an
inline function.
Based on this work, Alex proposed the following patch series
https://lists.gnu.org/archive/html/qemu-devel/2016-01/msg01136.html
that reduces code duplication of the softmmu_helpers.
Suggested-by: Jani Kokkonen <address@hidden>
Suggested-by: Claudio Fontana <address@hidden>
Signed-off-by: Alvise Rigo <address@hidden>
---
softmmu_template.h | 66 ++++++++++++++++++++++++++++++++++++------------------
1 file changed, 44 insertions(+), 22 deletions(-)
diff --git a/softmmu_template.h b/softmmu_template.h
index 7029a03..3d388ec 100644
--- a/softmmu_template.h
+++ b/softmmu_template.h
@@ -396,6 +396,26 @@ static inline void glue(helper_le_st_name,
_do_unl_access)(CPUArchState *env,
}
}
+static inline void glue(helper_le_st_name, _do_mmio_access)(CPUArchState *env,
+ DATA_TYPE val,
+ target_ulong addr,
+ TCGMemOpIdx oi,
+ unsigned mmu_idx,
+ int index,
+ uintptr_t retaddr)
+{
+ CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
+
+ if ((addr & (DATA_SIZE - 1)) != 0) {
+ glue(helper_le_st_name, _do_unl_access)(env, val, addr, mmu_idx,
+ oi, retaddr);
+ }
+ /* ??? Note that the io helpers always read data in the target
+ byte ordering. We should push the LE/BE request down into io. */
+ val = TGT_LE(val);
+ glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr);
+}
+
void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
TCGMemOpIdx oi, uintptr_t retaddr)
{
@@ -423,17 +443,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong
addr, DATA_TYPE val,
/* Handle an IO access. */
if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
- CPUIOTLBEntry *iotlbentry;
- if ((addr & (DATA_SIZE - 1)) != 0) {
- glue(helper_le_st_name, _do_unl_access)(env, val, addr, mmu_idx,
- oi, retaddr);
- }
- iotlbentry = &env->iotlb[mmu_idx][index];
-
- /* ??? Note that the io helpers always read data in the target
- byte ordering. We should push the LE/BE request down into io. */
- val = TGT_LE(val);
- glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr);
+ glue(helper_le_st_name, _do_mmio_access)(env, val, addr, oi,
+ mmu_idx, index, retaddr);
return;
}
@@ -488,6 +499,26 @@ static inline void glue(helper_be_st_name,
_do_unl_access)(CPUArchState *env,
}
}
+static inline void glue(helper_be_st_name, _do_mmio_access)(CPUArchState *env,
+ DATA_TYPE val,
+ target_ulong addr,
+ TCGMemOpIdx oi,
+ unsigned mmu_idx,
+ int index,
+ uintptr_t retaddr)
+{
+ CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
+
+ if ((addr & (DATA_SIZE - 1)) != 0) {
+ glue(helper_be_st_name, _do_unl_access)(env, val, addr, mmu_idx,
+ oi, retaddr);
+ }
+ /* ??? Note that the io helpers always read data in the target
+ byte ordering. We should push the LE/BE request down into io. */
+ val = TGT_BE(val);
+ glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr);
+}
+
void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
TCGMemOpIdx oi, uintptr_t retaddr)
{
@@ -515,17 +546,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong
addr, DATA_TYPE val,
/* Handle an IO access. */
if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
- CPUIOTLBEntry *iotlbentry;
- if ((addr & (DATA_SIZE - 1)) != 0) {
- glue(helper_be_st_name, _do_unl_access)(env, val, addr, mmu_idx,
- oi, retaddr);
- }
- iotlbentry = &env->iotlb[mmu_idx][index];
-
- /* ??? Note that the io helpers always read data in the target
- byte ordering. We should push the LE/BE request down into io. */
- val = TGT_BE(val);
- glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr);
+ glue(helper_be_st_name, _do_mmio_access)(env, val, addr, oi,
+ mmu_idx, index, retaddr);
return;
}
--
2.7.0
- [Qemu-devel] [RFC v7 00/16] Slow-path for atomic instruction translation, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 05/16] softmmu: Add new TLB_EXCL flag, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 02/16] softmmu: Simplify helper_*_st_name, wrap unaligned code, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 03/16] softmmu: Simplify helper_*_st_name, wrap MMIO code,
Alvise Rigo <=
- [Qemu-devel] [RFC v7 06/16] qom: cpu: Add CPUClass hooks for exclusive range, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 08/16] softmmu: Honor the new exclusive bitmap, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 01/16] exec.c: Add new exclusive bitmap to ram_list, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 04/16] softmmu: Simplify helper_*_st_name, wrap RAM code, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 09/16] softmmu: Include MMIO/invalid exclusive accesses, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 15/16] target-arm: cpu64: use custom set_excl hook, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 10/16] softmmu: Protect MMIO exclusive range, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 14/16] target-arm: translate: Use ld/st excl for atomic insns, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 16/16] target-arm: aarch64: add atomic instructions, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 07/16] softmmu: Add helpers for a new slowpath, Alvise Rigo, 2016/01/29