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[Qemu-devel] [RFC v7 15/16] target-arm: cpu64: use custom set_excl hook
From: |
Alvise Rigo |
Subject: |
[Qemu-devel] [RFC v7 15/16] target-arm: cpu64: use custom set_excl hook |
Date: |
Fri, 29 Jan 2016 10:32:44 +0100 |
In aarch64 the LDXP/STXP instructions allow to perform up to 128 bits
exclusive accesses. However, due to a softmmu limitation, such wide
accesses are not allowed.
To workaround this limitation, we need to support LoadLink instructions
that cover at least 128 consecutive bits (see the next patch for more
details).
Suggested-by: Jani Kokkonen <address@hidden>
Suggested-by: Claudio Fontana <address@hidden>
Signed-off-by: Alvise Rigo <address@hidden>
---
target-arm/cpu64.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index cc177bb..1d45e66 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -287,6 +287,13 @@ static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
}
}
+static void aarch64_set_excl_range(CPUState *cpu, hwaddr addr, hwaddr size)
+{
+ cpu->excl_protected_range.begin = addr;
+ /* At least cover 128 bits for a STXP access (two paired doublewords
case)*/
+ cpu->excl_protected_range.end = addr + 16;
+}
+
static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
@@ -297,6 +304,7 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void
*data)
cc->gdb_write_register = aarch64_cpu_gdb_write_register;
cc->gdb_num_core_regs = 34;
cc->gdb_core_xml_file = "aarch64-core.xml";
+ cc->cpu_set_excl_protected_range = aarch64_set_excl_range;
}
static void aarch64_cpu_register(const ARMCPUInfo *info)
--
2.7.0
- [Qemu-devel] [RFC v7 00/16] Slow-path for atomic instruction translation, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 05/16] softmmu: Add new TLB_EXCL flag, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 02/16] softmmu: Simplify helper_*_st_name, wrap unaligned code, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 03/16] softmmu: Simplify helper_*_st_name, wrap MMIO code, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 06/16] qom: cpu: Add CPUClass hooks for exclusive range, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 08/16] softmmu: Honor the new exclusive bitmap, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 01/16] exec.c: Add new exclusive bitmap to ram_list, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 04/16] softmmu: Simplify helper_*_st_name, wrap RAM code, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 09/16] softmmu: Include MMIO/invalid exclusive accesses, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 15/16] target-arm: cpu64: use custom set_excl hook,
Alvise Rigo <=
- [Qemu-devel] [RFC v7 10/16] softmmu: Protect MMIO exclusive range, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 14/16] target-arm: translate: Use ld/st excl for atomic insns, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 16/16] target-arm: aarch64: add atomic instructions, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 07/16] softmmu: Add helpers for a new slowpath, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 12/16] configure: Use slow-path for atomic only when the softmmu is enabled, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 13/16] softmmu: Add history of excl accesses, Alvise Rigo, 2016/01/29
- [Qemu-devel] [RFC v7 11/16] tcg: Create new runtime helpers for excl accesses, Alvise Rigo, 2016/01/29