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Re: [Qemu-devel] [PATCH 1/8] target-arm: Properly support EL2 and EL3 in
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 1/8] target-arm: Properly support EL2 and EL3 in arm_el_is_aa64() |
Date: |
Fri, 29 Jan 2016 17:05:47 +0000 |
On 29 January 2016 at 16:45, Sergey Fedorov <address@hidden> wrote:
> On 14.01.2016 21:34, Peter Maydell wrote:
>> Support EL2 and EL3 in arm_el_is_aa64() by implementing the
>> logic for checking the SCR_EL3 and HCR_EL2 register-width bits
>> as appropriate to determine the register width of lower exception
>> levels.
>
> Reviewed-by: Sergey Fedorov <address@hidden>
Thanks for the review, but this series went into master last week :-)
-- PMM
- Re: [Qemu-devel] [PATCH 3/8] target-arm: Use a single entry point for AArch64 and AArch32 exceptions, (continued)
Re: [Qemu-devel] [PATCH 1/8] target-arm: Properly support EL2 and EL3 in arm_el_is_aa64(), Sergey Fedorov, 2016/01/29
[Qemu-devel] [PATCH 4/8] target-arm: Pull semihosting handling out to arm_cpu_do_interrupt(), Peter Maydell, 2016/01/14
[Qemu-devel] [PATCH 8/8] target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode, Peter Maydell, 2016/01/14
[Qemu-devel] [PATCH 2/8] target-arm: Move aarch64_cpu_do_interrupt() to helper.c, Peter Maydell, 2016/01/14
[Qemu-devel] [PATCH 6/8] target-arm: Handle exception return from AArch64 to non-EL0 AArch32, Peter Maydell, 2016/01/14