[Qemu-devel] [PATCH 0/9] mips: implement Inter-Thread Communication Unit

[Leon Alrae]

Inter-Thread Communication Unit (ITU) provides ITC storage which is a
gating storage mechanism for efficient communication and data transfer
between threads.

Each 64-bit location or "cell" within ITC space appears at multiple
consecutive addresses, or "views", distinguished by bits [6:3] of the
load/store target address. Each view can have distinct semantics. For
example in some views a load from a cell which is empty causes the
thread issuing the load to be blocked until the cell is written to
by a store from another thread.

In this implementation there are two kinds of storage cells (four-entry
FIFO queues and single-entry Semaphore cells) and six views (Bypass,
Control, E/F Synchronized, E/F Try, P/V Synchronized and P/V Try).

ITU object contains two memory regions: ITC Storage which is memory-mapped
and ITC Configuration Tags which are accessible directly from the CPU via
Cache instruction. Guest can remap the ITC storage by writing into ITC
Configuration Tags.
If thread is supposed to be blocked then it is marked as halted and it exits
the cpu loop. On the wake-up the thread will be restarted from the last
instruction.
This patchset does not implement Gating Storage exceptions. Also it does not
implement the behaviour of SC instruction which should indicate
success/failure of the access in E/F Try view.

In QEMU the ITU is available to any multi-threaded CPU, i.e. 34Kf and
MIPS64R6-generic. Therefore this patchset applies on to top of the other
patch introducing R6 multi-threading support.

This feature has been divided into the following patches:

* patches 1 and 2: define an ITU object and initial data structures
* patches 3-6: implement ITC Views
* patch 7: add ITC block to malta board
* patch 8: minor fix for Cache instruction in R6
* patch 9: make changes in the CPU to access ITC Tags

Feedback is welcome!

Thanks,
Leon

Leon Alrae (9):
  hw/mips: implement ITC Configuration Tags
  hw/mips: add ITC Storage Cells
  hw/mips: implement ITC Storage - Control View
  hw/mips: implement ITC Storage - Empty/Full Sync and Try Views
  hw/mips: implement ITC Storage - P/V Sync and Try Views
  hw/mips: implement ITC Storage - Bypass View
  hw/mips_malta: make ITU available to multi-threading processors
  target-mips: check CP0 enabled for CACHE instruction also in R6
  target-mips: make ITC Configuration Tags accessible to the CPU

 default-configs/mips-softmmu.mak     |   1 +
 default-configs/mips64-softmmu.mak   |   1 +
 default-configs/mips64el-softmmu.mak |   1 +
 default-configs/mipsel-softmmu.mak   |   1 +
 hw/mips/mips_malta.c                 |  53 ++++
 hw/misc/Makefile.objs                |   1 +
 hw/misc/mips_itu.c                   | 515 +++++++++++++++++++++++++++++++++++
 include/hw/misc/mips_itu.h           |  72 +++++
 target-mips/cpu.h                    |   8 +-
 target-mips/helper.h                 |   3 +
 target-mips/op_helper.c              |  40 ++-
 target-mips/translate.c              |  63 ++++-
 12 files changed, 747 insertions(+), 12 deletions(-)
 create mode 100644 hw/misc/mips_itu.c
 create mode 100644 include/hw/misc/mips_itu.h

-- 
2.1.0