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[Qemu-devel] [PATCH 8/9] target-mips: check CP0 enabled for CACHE instru
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PATCH 8/9] target-mips: check CP0 enabled for CACHE instruction also in R6 |
Date: |
Wed, 3 Feb 2016 16:56:50 +0000 |
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index c6e2951..3fb3744 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -17179,6 +17179,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env,
DisasContext *ctx)
/* Treat as NOP. */
break;
case R6_OPC_CACHE:
+ check_cp0_enabled(ctx);
/* Treat as NOP. */
break;
case R6_OPC_SC:
--
2.1.0
- [Qemu-devel] [PATCH 0/9] mips: implement Inter-Thread Communication Unit, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 1/9] hw/mips: implement ITC Configuration Tags, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 2/9] hw/mips: add ITC Storage Cells, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 3/9] hw/mips: implement ITC Storage - Control View, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 4/9] hw/mips: implement ITC Storage - Empty/Full Sync and Try Views, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 5/9] hw/mips: implement ITC Storage - P/V Sync and Try Views, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 8/9] target-mips: check CP0 enabled for CACHE instruction also in R6,
Leon Alrae <=
- [Qemu-devel] [PATCH 6/9] hw/mips: implement ITC Storage - Bypass View, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 7/9] hw/mips_malta: make ITU available to multi-threading processors, Leon Alrae, 2016/02/03
- [Qemu-devel] [PATCH 9/9] target-mips: make ITC Configuration Tags accessible to the CPU, Leon Alrae, 2016/02/03