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[Qemu-devel] [PULL 08/17] libvixl: Avoid std::abs() of 64-bit type
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 08/17] libvixl: Avoid std::abs() of 64-bit type |
Date: |
Wed, 3 Feb 2016 18:59:11 +0000 |
The std::abs() function did not get a version that works on
'long long' until C++11. Avoid it, so that we can compile on
32-bit platforms (where int64_t is 'long long') with older
compilers (which don't support C++11).
Reported-by: Franz-Josef Haider <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
disas/libvixl/vixl/a64/disasm-a64.cc | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/disas/libvixl/vixl/a64/disasm-a64.cc
b/disas/libvixl/vixl/a64/disasm-a64.cc
index 20caba4..7a58a5c 100644
--- a/disas/libvixl/vixl/a64/disasm-a64.cc
+++ b/disas/libvixl/vixl/a64/disasm-a64.cc
@@ -2688,8 +2688,12 @@ void Disassembler::AppendRegisterNameToOutput(const
Instruction* instr,
void Disassembler::AppendPCRelativeOffsetToOutput(const Instruction* instr,
int64_t offset) {
USE(instr);
+ uint64_t abs_offset = offset;
char sign = (offset < 0) ? '-' : '+';
- AppendToOutput("#%c0x%" PRIx64, sign, std::abs(offset));
+ if (offset < 0) {
+ abs_offset = -abs_offset;
+ }
+ AppendToOutput("#%c0x%" PRIx64, sign, abs_offset);
}
--
1.9.1
- [Qemu-devel] [PULL 00/17] target-arm queue, Peter Maydell, 2016/02/03
- [Qemu-devel] [PULL 01/17] virt-acpi-build: add always-on property for timer, Peter Maydell, 2016/02/03
- [Qemu-devel] [PULL 16/17] arm/boot: move highbank secure board setup code to common routine, Peter Maydell, 2016/02/03
- [Qemu-devel] [PULL 17/17] raspi: add raspberry pi 2 machine, Peter Maydell, 2016/02/03
- [Qemu-devel] [PULL 15/17] bcm2836: add bcm2836 SoC device, Peter Maydell, 2016/02/03
- [Qemu-devel] [PULL 05/17] target-arm: Rename check_s2_startlevel to check_s2_mmu_setup, Peter Maydell, 2016/02/03
- [Qemu-devel] [PULL 08/17] libvixl: Avoid std::abs() of 64-bit type,
Peter Maydell <=
- [Qemu-devel] [PULL 12/17] bcm2835_ic: add bcm2835 interrupt controller, Peter Maydell, 2016/02/03
- [Qemu-devel] [PULL 11/17] bcm2835_property: add bcm2835 property channel, Peter Maydell, 2016/02/03
- [Qemu-devel] [PULL 02/17] target-arm: Make various system registers visible to EL3, Peter Maydell, 2016/02/03
- [Qemu-devel] [PULL 09/17] target-arm: Don't report presence of EL2 if it doesn't exist, Peter Maydell, 2016/02/03
- [Qemu-devel] [PULL 03/17] hw/arm: Setup EL1 and EL2 in AArch64 mode for 64bit Linux boots, Peter Maydell, 2016/02/03
- [Qemu-devel] [PULL 04/17] target-arm: Apply S2 MMU startlevel table size check to AArch64, Peter Maydell, 2016/02/03
- [Qemu-devel] [PULL 10/17] bcm2835_mbox: add BCM2835 mailboxes, Peter Maydell, 2016/02/03
- [Qemu-devel] [PULL 14/17] bcm2836_control: add bcm2836 ARM control logic, Peter Maydell, 2016/02/03
- [Qemu-devel] [PULL 06/17] target-arm: Implement the S2 MMU inputsize > pamax check, Peter Maydell, 2016/02/03
- [Qemu-devel] [PULL 07/17] arm: virt-acpi: each MADT.GICC entry as enabled unconditionally, Peter Maydell, 2016/02/03