[Qemu-devel] [PATCH v2 5/5] target-arm: Unmask PMU bits in debug feature register

[Alistair Francis]

The previously missing registers are now present in QEMU.

Signed-off-by: Christopher Covington <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---

 target-arm/helper.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index b4bf6fa..1775768 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4267,12 +4267,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
               .access = PL1_R, .type = ARM_CP_CONST,
-              /* We mask out the PMUVer field, because we don't currently
-               * implement the PMU. Not advertising it prevents the guest
-               * from trying to use it and getting UNDEFs on registers we
-               * don't implement.
-               */
-              .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
+              .resetvalue = cpu->id_aa64dfr0 },
             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
               .access = PL1_R, .type = ARM_CP_CONST,
-- 
2.5.0