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[Qemu-devel] [PATCH v3 3/3] target-arm: Add PMUSERENR_EL0 register
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v3 3/3] target-arm: Add PMUSERENR_EL0 register |
Date: |
Tue, 9 Feb 2016 15:47:21 -0800 |
The Linux kernel accesses this register early in its setup.
Signed-off-by: Christopher Covington <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 1778431..f700189 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1027,6 +1027,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
.resetvalue = 0,
.writefn = pmuserenr_write, .raw_writefn = raw_write },
+ { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
+ .access = PL0_R | PL1_RW, .type = ARM_CP_ALIAS,
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
+ .resetvalue = 0,
+ .writefn = pmuserenr_write, .raw_writefn = raw_write },
{ .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 =
1,
.access = PL1_RW,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
--
2.5.0