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[Qemu-devel] [PATCH v2 08/16] tcg-mips: Adjust prologue for mips64
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 08/16] tcg-mips: Adjust prologue for mips64 |
Date: |
Mon, 15 Feb 2016 14:42:26 +1100 |
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/mips/tcg-target.c | 56 ++++++++++++++++++++++++---------------------------
1 file changed, 26 insertions(+), 30 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index d1266ef..4a3f11a 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -716,16 +716,6 @@ static inline void tcg_out_st(TCGContext *s, TCGType type,
TCGReg arg,
tcg_out_ldst(s, opc, arg, arg1, arg2);
}
-static inline void tcg_out_addi(TCGContext *s, TCGReg reg, TCGArg val)
-{
- if (val == (int16_t)val) {
- tcg_out_opc_imm(s, OPC_ADDIU, reg, reg, val);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, val);
- tcg_out_opc_reg(s, OPC_ADDU, reg, reg, TCG_TMP0);
- }
-}
-
static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
bool cbh, bool is_sub)
@@ -2224,42 +2214,48 @@ static tcg_insn_unit *align_code_ptr(TCGContext *s)
return s->code_ptr;
}
+/* Stack frame parameters. */
+#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
+#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
+#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
+
+#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
+ + TCG_TARGET_STACK_ALIGN - 1) \
+ & -TCG_TARGET_STACK_ALIGN)
+#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
+
+/* We're expecting to be able to use an immediate for frame allocation. */
+QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
+
/* Generate global QEMU prologue and epilogue code */
static void tcg_target_qemu_prologue(TCGContext *s)
{
- int i, frame_size;
-
- /* reserve some stack space, also for TCG temps. */
- frame_size = ARRAY_SIZE(tcg_target_callee_save_regs) * 4
- + TCG_STATIC_CALL_ARGS_SIZE
- + CPU_TEMP_BUF_NLONGS * sizeof(long);
- frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
- ~(TCG_TARGET_STACK_ALIGN - 1);
- tcg_set_frame(s, TCG_REG_SP, ARRAY_SIZE(tcg_target_callee_save_regs) * 4
- + TCG_STATIC_CALL_ARGS_SIZE,
- CPU_TEMP_BUF_NLONGS * sizeof(long));
+ int i;
+
+ tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
/* TB prologue */
- tcg_out_addi(s, TCG_REG_SP, -frame_size);
- for(i = 0 ; i < ARRAY_SIZE(tcg_target_callee_save_regs) ; i++) {
- tcg_out_st(s, TCG_TYPE_I32, tcg_target_callee_save_regs[i],
- TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE + i * 4);
+ tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
+ for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
+ tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
+ TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
}
/* Call generated code */
tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
+ /* delay slot */
tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
- tb_ret_addr = s->code_ptr;
/* TB epilogue */
- for(i = 0 ; i < ARRAY_SIZE(tcg_target_callee_save_regs) ; i++) {
- tcg_out_ld(s, TCG_TYPE_I32, tcg_target_callee_save_regs[i],
- TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE + i * 4);
+ tb_ret_addr = s->code_ptr;
+ for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
+ tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
+ TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
}
tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
/* delay slot */
- tcg_out_addi(s, TCG_REG_SP, frame_size);
+ tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
if (use_mips32r2_instructions) {
return;
--
2.5.0
- [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements, Richard Henderson, 2016/02/14
- [Qemu-devel] [PATCH v2 01/16] tcg-mips: Always use tcg_debug_assert, Richard Henderson, 2016/02/14
- [Qemu-devel] [PATCH v2 02/16] tcg-mips: Move bswap code to a subroutine, Richard Henderson, 2016/02/14
- [Qemu-devel] [PATCH v2 03/16] tcg-mips: Add mips64 opcodes, Richard Henderson, 2016/02/14
- [Qemu-devel] [PATCH v2 05/16] tcg-mips: Add bswap32u and bswap64, Richard Henderson, 2016/02/14
- [Qemu-devel] [PATCH v2 06/16] tcg-mips: Adjust move functions for mips64, Richard Henderson, 2016/02/14
- [Qemu-devel] [PATCH v2 04/16] tcg-mips: Support 64-bit opcodes, Richard Henderson, 2016/02/14
- [Qemu-devel] [PATCH v2 07/16] tcg-mips: Adjust load/store functions for mips64, Richard Henderson, 2016/02/14
- [Qemu-devel] [PATCH v2 08/16] tcg-mips: Adjust prologue for mips64,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 09/16] tcg-mips: Add tcg unwind info, Richard Henderson, 2016/02/14
- [Qemu-devel] [PATCH v2 10/16] tcg-mips: Adjust qemu_ld/st for mips64, Richard Henderson, 2016/02/14
- [Qemu-devel] [PATCH v2 11/16] tcg-mips: Adjust calling conventions for mips64, Richard Henderson, 2016/02/14
- [Qemu-devel] [PATCH v2 12/16] tcg-mips: Improve tcg_out_movi for mips64, Richard Henderson, 2016/02/14
- [Qemu-devel] [PATCH v2 13/16] tcg-mips: Use mips64r6 instructions in tcg_out_ldst, Richard Henderson, 2016/02/14
- [Qemu-devel] [PATCH v2 14/16] tcg-mips: Use mips64r6 instructions in constant addition, Richard Henderson, 2016/02/14
- [Qemu-devel] [PATCH v2 16/16] tcg-mips: Use mipsr6 instructions in calls, Richard Henderson, 2016/02/14
- [Qemu-devel] [PATCH v2 15/16] tcg-mips: Use mipsr6 instructions in branches, Richard Henderson, 2016/02/14
- Re: [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements, Richard Henderson, 2016/02/14
- Re: [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements, Aurelien Jarno, 2016/02/28