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[Qemu-devel] [PULL 10/36] target-arm: Combine user-only and softmmu get/
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/36] target-arm: Combine user-only and softmmu get/set_r13_banked() |
Date: |
Thu, 18 Feb 2016 14:34:42 +0000 |
The user-mode versions of get/set_r13_banked() exist just to assert
if they're ever called -- the translate time code should never
emit calls to them because SRS from user mode always UNDEF.
There's no code in the softmmu versions that can't compile in
CONFIG_USER_ONLY, and the assertion is not particularly useful,
so combine the two functions rather than having completely split
versions under ifdefs.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
---
target-arm/op_helper.c | 19 -------------------
1 file changed, 19 deletions(-)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 053e9b6..cfdbc8d 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -457,24 +457,6 @@ void HELPER(set_user_reg)(CPUARMState *env, uint32_t
regno, uint32_t val)
}
}
-#if defined(CONFIG_USER_ONLY)
-void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
-{
- ARMCPU *cpu = arm_env_get_cpu(env);
-
- cpu_abort(CPU(cpu), "banked r13 write\n");
-}
-
-uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
-{
- ARMCPU *cpu = arm_env_get_cpu(env);
-
- cpu_abort(CPU(cpu), "banked r13 read\n");
- return 0;
-}
-
-#else
-
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
{
if ((env->uncached_cpsr & CPSR_M) == mode) {
@@ -492,7 +474,6 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t
mode)
return env->banked_r13[bank_number(mode)];
}
}
-#endif
void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t
syndrome,
uint32_t isread)
--
1.9.1
- [Qemu-devel] [PULL 00/36] target-arm queue, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 04/36] target-arm: Implement MDCR_EL2.TDRA traps, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 12/36] target-arm: Add the pmceid0 and pmceid1 registers, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 36/36] hw/timer: QOM'ify pxa2xx_timer, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 13/36] target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 11/36] target-arm: UNDEF in the UNPREDICTABLE SRS-from-System case, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 10/36] target-arm: Combine user-only and softmmu get/set_r13_banked(),
Peter Maydell <=
- [Qemu-devel] [PULL 35/36] hw/timer: QOM'ify pl031, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 33/36] hw/timer: QOM'ify exynos4210_pwm, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 31/36] hw/timer: QOM'ify arm_timer (pass 2), Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 32/36] hw/timer: QOM'ify exynos4210_mct, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 29/36] hw/sd: use guest error logging rather than fprintf to stderr, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 26/36] hw/sd/pxa2xx_mmci: Add reset function, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 27/36] hw/sd: implement CMD23 (SET_BLOCK_COUNT) for MMC compatibility, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 18/36] hw/sd/sd.c: QOMify, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 15/36] ARM: PL061: Clear PL061 device state after reset, Peter Maydell, 2016/02/18
- [Qemu-devel] [PULL 01/36] target-arm: correct CNTFRQ access rights, Peter Maydell, 2016/02/18