Re: [Qemu-devel] [V4 3/4] hw/i386: ACPI table for AMD IO MMU

[Jan Kiszka]

On 2016-02-17 20:09, David Kiarie wrote:
> Add IVRS table for AMD IO MMU. Also reverve MMIO
> region for IO MMU via ACPI
> 
> Signed-off-by: David Kiarie <address@hidden>
> ---
>  hw/i386/acpi-build.c        | 98 
> ++++++++++++++++++++++++++++++++++++++++-----
>  include/hw/acpi/acpi-defs.h | 55 +++++++++++++++++++++++++
>  2 files changed, 142 insertions(+), 11 deletions(-)
> 
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> index 739cfa3..b8cd091 100644
> --- a/hw/i386/acpi-build.c
> +++ b/hw/i386/acpi-build.c
> @@ -51,6 +51,7 @@
>  #include "hw/pci/pci_bus.h"
>  #include "hw/pci-host/q35.h"
>  #include "hw/i386/intel_iommu.h"
> +#include "hw/i386/amd_iommu.h"
>  #include "hw/timer/hpet.h"
>  
>  #include "hw/acpi/aml-build.h"
> @@ -121,6 +122,12 @@ typedef struct AcpiBuildPciBusHotplugState {
>      bool pcihp_bridge_en;
>  } AcpiBuildPciBusHotplugState;
>  
> +typedef enum iommu_type {
> +    TYPE_AMD,
> +    TYPE_INTEL,
> +    TYPE_NONE
> +} iommu_type;
> +
>  static
>  int acpi_add_cpu_info(Object *o, void *opaque)
>  {
> @@ -2423,6 +2430,78 @@ build_dmar_q35(GArray *table_data, GArray *linker)
>  }
>  
>  static void
> +build_amd_iommu(GArray *table_data, GArray *linker)
> +{
> +    int iommu_start = table_data->len;
> +    bool iommu_ambig;
> +
> +    AcpiAMDIOMMUIVRS *ivrs;
> +    AcpiAMDIOMMUHardwareUnit *iommu;
> +
> +    /* IVRS definition */
> +    ivrs = acpi_data_push(table_data, sizeof(*ivrs));
> +    ivrs->revision = cpu_to_le16(ACPI_IOMMU_IVRS_TYPE);
> +    ivrs->length = cpu_to_le16((sizeof(*ivrs) + sizeof(*iommu)));
> +    ivrs->v_common_info = cpu_to_le64(AMD_IOMMU_HOST_ADDRESS_WIDTH << 8);
> +
> +    AMDIOMMUState *s = (AMDIOMMUState *)object_resolve_path_type("",
> +                        TYPE_AMD_IOMMU_DEVICE, &iommu_ambig);
> +
> +    /* IVDB definition - type 10h */
> +    iommu = acpi_data_push(table_data, sizeof(*iommu));
> +    if (!iommu_ambig) {
> +        iommu->type = cpu_to_le16(0x10);
> +        /* IVHD flags */
> +        iommu->flags = cpu_to_le16(iommu->flags);
> +        iommu->flags = cpu_to_le16(IVHD_HT_TUNEN | IVHD_PPRSUP | 
> IVHD_IOTLBSUP
> +                       | IVHD_PREFSUP);
> +        iommu->length = cpu_to_le16(sizeof(*iommu));
> +        iommu->device_id = cpu_to_le16(PCI_DEVICE_ID_RD890_IOMMU);
> +        iommu->capability_offset = cpu_to_le16(s->capab_offset);
> +        iommu->mmio_base = cpu_to_le64(s->mmio.addr);
> +        iommu->pci_segment = 0;
> +        iommu->interrupt_info = 0;
> +        /* EFR features */
> +        iommu->efr_register = cpu_to_le64(IVHD_EFR_GTSUP | IVHD_EFR_HATS
> +                              | IVHD_EFR_GATS);
> +        iommu->efr_register = cpu_to_le64(iommu->efr_register);
> +        /* device entries */
> +        memset(iommu->dev_entries, 0, 20);
> +        /* Add device flags here
> +         *  This is are 4-byte device entries currently reporting the range 
> of
> +         *  devices 00h - ffffh; all devices
> +         *
> +         *  Device setting affecting all devices should be made here
> +         *
> +         *  Refer to
> +         *  (http://developer.amd.com/wordpress/media/2012/10/488821.pdf)
> +         *  5.2.2.1
> +         */
> +        iommu->dev_entries[12] = 3;
> +        iommu->dev_entries[16] = 4;
> +        iommu->dev_entries[17] = 0xff;
> +        iommu->dev_entries[18] = 0xff;
> +    }
> +
> +    build_header(linker, table_data, (void *)(table_data->data + 
> iommu_start),
> +                 "IVRS", table_data->len - iommu_start, 1, NULL);

Requires rebasing over master (to append another NULL here).

Jan

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