Re: [Qemu-devel] [PATCH] hw/intc/arm_gic.c: Implement GICv2 GICC_DIR

[Peter Maydell]

On 23 February 2016 at 18:50, Peter Maydell <address@hidden> wrote:
> The GICv2 introduces a new CPU interface register GICC_DIR, which
> allows an OS to split the "priority drop" and "deactivate interrupt"
> parts of interrupt completion. Implement this register.
> (Note that the register is at offset 0x1000 in the CPU interface,
> which means it is on a different 4K page from all the other registers.)
>
> Signed-off-by: Peter Maydell <address@hidden>

> +static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs 
> attrs)
> +{
> +    int cm = 1 << cpu;
> +    int group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);
> +
> +    if (!gic_eoi_split(s, cpu, attrs)) {
> +        /* This is UNPREDICTABLE; we choose to ignore it */
> +        qemu_log_mask(LOG_GUEST_ERROR,
> +                      "gic_deactivate_irq: GICC_DIR write when EOIMode 
> clear");
> +        return;
> +    }
> +
> +    if (s->security_extn && !attrs.secure && !group) {
> +        DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq);
> +        return;
> +    }
> +
> +    GIC_CLEAR_ACTIVE(irq, cm);
> +    gic_update(s);

Whoops, this gic_update() call should be deleted, because the caller
will do a gic_update anyway. (The extra call is harmless but unnecessary.)

thanks
-- PMM