[Qemu-devel] [PATCH 3/7] target-tricore: add add.f/sub.f instructions

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <address@hidden>
---
 target-tricore/fpu_helper.c | 31 +++++++++++++++++++++++++++++++
 target-tricore/helper.h     |  2 ++
 target-tricore/translate.c  |  6 ++++++
 3 files changed, 39 insertions(+)

diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index ddf877e..b840c20 100644
--- a/target-tricore/fpu_helper.c
+++ b/target-tricore/fpu_helper.c
@@ -81,3 +81,34 @@ static inline void f_set_flags(CPUTriCoreState *env)
     set_flush_to_zero(1, &env->fp_status);
     set_float_exception_flags(0, &env->fp_status);
 }
+
+#define FADD_SUB(name)                                                         
\
+uint32_t helper_f##name(CPUTriCoreState *env, uint32_t r1, uint32_t r2)        
\
+{                                                                              
\
+    float32 arg1 = make_float32(r1);                                           
\
+    float32 arg2 = make_float32(r2);                                           
\
+    float32 f_result;                                                          
\
+                                                                               
\
+    f_set_flags(env);                                                          
\
+                                                                               
\
+    arg1 = float32_squash_input_denormal(arg1, &env->fp_status);               
\
+    arg2 = float32_squash_input_denormal(arg2, &env->fp_status);               
\
+                                                                               
\
+    if (float32_is_any_nan(arg1) || float32_is_any_nan(arg2)) {                
\
+        f_result = QUIET_NAN;                                                  
\
+        if (float32_is_signaling_nan(arg1) ||                                  
\
+            float32_is_signaling_nan(arg2)) {                                  
\
+            env->fp_status.float_exception_flags |= float_flag_invalid;        
\
+        }                                                                      
\
+    } else if (f_is_pos_inf(arg1) && f_is_neg_inf(arg2)) {                     
\
+        f_result = ADD_NAN;                                                    
\
+    } else if (f_is_pos_inf(arg2) && f_is_neg_inf(arg1)) {                     
\
+        f_result = ADD_NAN;                                                    
\
+    } else {                                                                   
\
+        f_result = float32_##name(arg1, arg2 , &env->fp_status);               
\
+    }                                                                          
\
+    f_update_psw_flags(env, false);                                            
\
+    return (uint32_t)f_result;                                                 
\
+}
+FADD_SUB(add)
+FADD_SUB(sub)
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index 2c8ed78..2f4a2bb 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -105,6 +105,8 @@ DEF_HELPER_FLAGS_1(parity, TCG_CALL_NO_RWG_SE, i32, i32)
 /* float */
 DEF_HELPER_FLAGS_4(pack, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32)
 DEF_HELPER_1(unpack, i64, i32)
+DEF_HELPER_3(fadd, i32, env, i32, i32)
+DEF_HELPER_3(fsub, i32, env, i32, i32)
 /* dvinit */
 DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)
 DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 84313d2..04620a7 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -7061,6 +7061,12 @@ static void decode_rrr_divide(CPUTriCoreState *env, 
DisasContext *ctx)
         gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
                         cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
         break;
+    case OPC2_32_RRR_ADD_F:
+        gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
+        break;
+    case OPC2_32_RRR_SUB_F:
+        gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
+        break;
     default:
         generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
     }
-- 
2.7.2