Re: [Qemu-devel] [Qemu-ppc] [PATCH 72/77] ppc: A couple more dummy POWER8 Book4 regs

[Cédric Le Goater]

On 03/02/2016 09:30 PM, Thomas Huth wrote:
> On 11.11.2015 01:28, Benjamin Herrenschmidt wrote:
>> WORT and PID this time
>>
>> Signed-off-by: Benjamin Herrenschmidt <address@hidden>
>> ---
>>  target-ppc/cpu.h            |  2 ++
>>  target-ppc/translate_init.c | 16 ++++++++++++----
>>  2 files changed, 14 insertions(+), 4 deletions(-)
>>
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index aa328a7..6179fbc 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -1363,6 +1363,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, 
>> bool ifetch)
>>  #define SPR_AMR               (0x01D)
>>  #define SPR_ACOP              (0x01F)
>>  #define SPR_BOOKE_PID         (0x030)
>> +#define SPR_BOOKS_PID         (0x030)
>>  #define SPR_BOOKE_DECAR       (0x036)
>>  #define SPR_BOOKE_CSRR0       (0x03A)
>>  #define SPR_BOOKE_CSRR1       (0x03B)
>> @@ -1716,6 +1717,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, 
>> bool ifetch)
>>  #define SPR_POWER_SPMC1       (0x37C)
>>  #define SPR_POWER_SPMC2       (0x37D)
>>  #define SPR_POWER_MMCRS       (0x37E)
>> +#define SPR_WORT              (0x37F)
>>  #define SPR_PPR               (0x380)
>>  #define SPR_750_GQR0          (0x390)
>>  #define SPR_440_DNV0          (0x390)
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index 4ec532c..bfdf028 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -8226,10 +8226,18 @@ static void gen_spr_power8_book4(CPUPPCState *env)
>>                      &spr_read_generic, SPR_NOACCESS,
>>                      &spr_read_generic, &spr_write_generic,
>>                      0);
>> -    spr_register(env, SPR_ACOP, "ACOP",
>> -                 SPR_NOACCESS, SPR_NOACCESS,
>> -                 &spr_read_generic, &spr_write_generic,
>> -                 0);
>> +    spr_register_kvm(env, SPR_ACOP, "ACOP",
>> +                     SPR_NOACCESS, SPR_NOACCESS,
>> +                     &spr_read_generic, &spr_write_generic,
>> +                     KVM_REG_PPC_ACOP, 0);
>> +    spr_register_kvm(env, SPR_BOOKS_PID, "PID",
>> +                     SPR_NOACCESS, SPR_NOACCESS,
>> +                     &spr_read_generic, &spr_write_generic,
>> +                     KVM_REG_PPC_PID, 0);
>> +    spr_register_kvm(env, SPR_WORT, "WORT",
>> +                     SPR_NOACCESS, SPR_NOACCESS,
>> +                     &spr_read_generic, &spr_write_generic,
>> +                     KVM_REG_PPC_WORT, 0);
>>  #endif
>>  }
> 
> AFAICT all patches where you define new SPRs with spr_register_kvm[_hv]
> are also important independently of the rest of your patch series -
> otherwise these registers are currently lost during migration since they
> are not sync'ed with the KVM part in the kernel right now.
> 
> So if you've got some spare time, could you maybe extract all those
> patches that define new SPRs with spr_register_kvm[_hv] and send them as
> a separate patch series? That could help to fix future migration issues,
> and also would decrease the size of your really huge "Add native POWER8
> platform" patch series a little bit!

I have been maintaining a port of Ben's patchset on the latest qemu for other 
parts which should come after pnv is merged so I have a framework to test such 
sub-patchsets. I also have time to work on them but clearly not the expertise
in all areas !

What would be nice is to identify the most obvious ones, non controversial
that could be merged after a few iterations. I have a vague idea, the ones 
Reviewed-by David obviously being good candidates, the definition of new SPRs 
(even the dummy ones ?). That would remove 15/20 patches from the list below
I believe. May be more. I will go through the email thread to see what can 
be taken.

Would follow the xics patches (plenty of conflicts lately), mmu patches 
(but David has been working on this so it is shrinking), some pci fixes 
and helpers (should ping maintainers). We would then be at a point where 
only the core pnv patches are left. I think I am being very optimistic :) 

I can start with a first serie. Suggestions welcomed. List below.


 065f7f9b1e15 ppc: Fix CFAR updates
 f385d52fe9f2 ppc: Add slbfee. instruction
 2bf0d4f4239a ppc: Add dummy logmpp instruction
 8102a4cc9c30 ppc: Print HSRR0/HSRR1 in "info registers"
 730a9b4dc941 ppc: Add KVM numbers to some P8 SPRs
 48adf38e9cab ppc: A couple more dummy POWER8 Book4 regs
 bce7c738ec1b ppc: Add dummy ACOP SPR
 34f1af75e75e ppc: Add dummy CIABR SPR
 64f92045e284 ppc: Add dummy POWER8 PSPB SPR
 ab003604993b ppc: Add dummy POWER8 MPPR register
 b81cf8c41288 ppc: Add dummy write to VTB
 490af9c31d8b ppc: Add a few more P8 PMU SPRs
 84886e8c188d ppc: Add POWER8 IAMR register
 5046c10f9e58 ppc: Fix writing to AMR/UAMOR
 c188b86cac90 ppc: Initialize AMOR in PAPR mode
 ee62b5581094 ppc: Add dummy SPR_IC for POWER8
 83e02b2026ef ppc: SPURR & PURR are HV writeable and privileged
 906a513acb1a ppc: LPCR is a HV resource
 27f45e80a104 ppc: Add placeholder SPRs for DPDES and DHDES on P8
 c1fc6d316f87 ppc: Initial HDEC support
 9f5d6c607af5 ppc: Enforce setting MSR:EE,IR and DR when MSR:PR is set
 a356d76a11bb ppc: Fix conditions for delivering external interrupts to a guest
 6ba5e576d1cc ppc/pnv+spapr: Add "ibm,pa-features" property to the device-tree
 cf768bc434e5 ppc: Fix 64K pages support in full emulation
 dbd6e54fd9c5 ppc: Add proper real mode translation support
 7250469a21ce ppc: Cosmetic, align some comments
 d94d8c4e7b3f ppc: Use a helper to filter writes to LPCR
 0694e0d87fe3 ppc: Update LPCR definitions
 20596a008f27 ppc/pnv: Create a default PCI layout
 4b393cbdb438 ppc/pnv: Add model for Power8 PHB3 PCIe Host bridge
 fa93c24cd3dc pci: Don't call pci_irq_handler() for a negative intx
 8872d909a8fb pci: Use the new pci_can_add_device() to enforce devfn_min/max
 9204957062b8 qdev: Add a hook for a bus to device if it can add devices
 00b55e345926 pci-bridge: Set a supported devfn_min for bridge
 e53d84a2716a ppc/pnv: Add OCC model stub with interrupt support
 0b6c38406589 ppc/pnv: Add cut down PSI bridge model and hookup external 
interrupt
 2649daef3f73 ppc/pnv: Add LPC controller and hook it up with a UART and RTC
 81fff5adcc87 ppc/pnv: Wire up XICS native with PowerNV platform
 aed1f862f0cc ppc/xics: Add xics to the monitor "info pic" command
 8a9d65a58764 ppc/xics: Add "native" XICS subclass
 2f29b84050d0 ppc/xics: Split ICS into base class and "simple" implementation
 f16e1abac820 ppc/xics: Use a helper to add a new ICS
 8311defd2daa ppc/xics: Move xics_set_nr_irqs() to xics_spapr.c and xics_kvm.c
 80ff29cbe02c ppc/xics: An ICS with offset 0 is assumed to be uninitialized
 b051717058cd ppc/xics: Make the ICSState a list
 c1498ed62ab9 ppc/xics: Replace "icp" with "xics" in most places
 de147c5277ee ppc/xics: Remove unused xics_set_irq_type()
 e8322cdda768 ppc/xics: Implement H_IPOLL using an accessor
 14597dd4d7c5 ppc/xics: Move SPAPR specific code to a separate file
 ea78b4729fe7 ppc/xics: Rename existing XICS classe to XICS_SPAPR
 b68322388931 ppc/pnv: Add XSCOM infrastructure
 e567fa64df0a ppc/pnv: Add skeletton PowerNV platform
 a926d8369e26 ppc: Add P7/P8 Power Management instructions
 bba3bf8362cf ppc: Move exception generation code out of line
 15411d6de866 ppc: Turn a bunch of booleans from int to bool
 554cf2e208d4 ppc: Add real mode CI load/store instructions for P7 and P8
 e75b02f8786e ppc: Rework generation of priv and inval interrupts
 ec7fde6eb1a6 ppc: Fix generation if ISI/DSI vs. HV mode
 91d6d6b8c720 ppc: Fix POWER7 and POWER8 exception definitions
 886802ba3a7b ppc: Rework POWER7 & POWER8 exception model
 72a37f87f790 ppc: Add PPC_64H instruction flag to POWER7 and POWER8
 036b3623c02d ppc: Get out of emulation on SMT "OR" ops
 5bf1a7bf1e45 ppc: Fix sign extension issue in mtmsr(d) emulation
 fbac2f43e655 ppc: Change 'invalid' bit mask of tlbiel and tlbie
 f308c5b1006f ppc: tlbie, tlbia and tlbisync are HV only
 317658992d97 ppc: Better figure out if processor has HV mode
 e25b26973a4b ppc: Create cpu_ppc_set_papr() helper
 14bffe9681df ppc: Fix rfi/rfid/hrfi/... emulation
 fb21ea327c61 ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV
 35fd16185bea ppc: Add number of threads per core to the processor definition
 e408897526e9 ppc: Add a bunch of hypervisor SPRs to Book3s
 5b287e66c751 ppc: Add macros to register hypervisor mode SPRs
 295ccb0507dc ppc: Update SPR definitions
 ed011d4fb179 ppc: Do some batching of TCG tlb flushes
 048a18af1c8d ppc: Use split I/D mmu modes to avoid flushes on interrupts
 681fc8d20391 ppc: Remove MMU_MODEn_SUFFIX definitions
 065f7f9b1e15 ppc: Fix CFAR updates
 2d3b7c0164e1 Merge remote-tracking branch 
'remotes/amit-virtio-rng/tags/rng-for-2.6-1' into staging

>From :

 https://github.com/legoater/qemu/commits/powernv-ipmi

$ git diff 2d3b7c0164e1..065f7f9b1e15  | diffstat 
 default-configs/ppc64-softmmu.mak   |    5 
 hmp-commands-info.hx                |    2 
 hw/intc/Makefile.objs               |    2 
 hw/intc/xics.c                      |  727 +++++++-----------------
 hw/intc/xics_kvm.c                  |   91 +--
 hw/intc/xics_native.c               |  295 +++++++++
 hw/intc/xics_spapr.c                |  429 ++++++++++++++
 hw/pci-bridge/pci_bridge_dev.c      |    2 
 hw/pci-host/Makefile.objs           |    2 
 hw/pci-host/pnv_phb3.c              | 1084 ++++++++++++++++++++++++++++++++++++
 hw/pci-host/pnv_phb3_msi.c          |  354 +++++++++++
 hw/pci-host/pnv_phb3_pbcq.c         |  315 ++++++++++
 hw/pci-host/pnv_phb3_rc.c           |  130 ++++
 hw/pci/pci.c                        |   26 
 hw/ppc/Makefile.objs                |    2 
 hw/ppc/pnv.c                        |  864 ++++++++++++++++++++++++++++
 hw/ppc/pnv_lpc.c                    |  527 +++++++++++++++++
 hw/ppc/pnv_occ.c                    |  126 ++++
 hw/ppc/pnv_psi.c                    |  594 +++++++++++++++++++
 hw/ppc/pnv_xscom.c                  |  415 +++++++++++++
 hw/ppc/ppc.c                        |   31 -
 hw/ppc/spapr.c                      |   28 
 hw/ppc/spapr_events.c               |    8 
 hw/ppc/spapr_hcall.c                |   14 
 hw/ppc/spapr_pci.c                  |   12 
 hw/ppc/spapr_vio.c                  |    2 
 include/hw/pci-host/pnv_phb3.h      |  145 ++++
 include/hw/pci-host/pnv_phb3_regs.h |  505 ++++++++++++++++
 include/hw/pci-host/spapr.h         |    2 
 include/hw/pci/pci_bus.h            |    1 
 include/hw/ppc/pnv.h                |   67 ++
 include/hw/ppc/pnv_xscom.h          |   73 ++
 include/hw/ppc/ppc.h                |    2 
 include/hw/ppc/spapr.h              |    2 
 include/hw/ppc/spapr_vio.h          |    2 
 include/hw/ppc/xics.h               |   81 ++
 include/hw/qdev-core.h              |    1 
 linux-user/main.c                   |    1 
 monitor.c                           |    3 
 qdev-monitor.c                      |   13 
 target-ppc/cpu-qom.h                |    1 
 target-ppc/cpu.h                    |  148 ++++
 target-ppc/excp_helper.c            |  369 +++++++-----
 target-ppc/helper.h                 |    6 
 target-ppc/helper_regs.h            |   75 ++
 target-ppc/machine.c                |    5 
 target-ppc/mmu-hash32.c             |    4 
 target-ppc/mmu-hash64.c             |  344 +++++++++--
 target-ppc/mmu-hash64.h             |    1 
 target-ppc/mmu_helper.c             |   17 
 target-ppc/timebase_helper.c        |   10 
 target-ppc/translate.c              | 1013 ++++++++++++++++++---------------
 target-ppc/translate_init.c         |  738 ++++++++++++++++++++++--
 53 files changed, 8350 insertions(+), 1366 deletions(-)

Thanks,

C.