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[Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR
From: |
Cédric Le Goater |
Subject: |
[Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR |
Date: |
Mon, 14 Mar 2016 17:56:39 +0100 |
From: Benjamin Herrenschmidt <address@hidden>
We should implement HW breakpoint/watchpoint, qemu supports them...
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
---
target-ppc/cpu.h | 1 +
target-ppc/translate_init.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 5203cc6a3bfb..9e1ef10b7dc6 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1400,6 +1400,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool
ifetch)
#define SPR_DAWR (0x0B4)
#define SPR_MPPR (0x0B8)
#define SPR_RPR (0x0BA)
+#define SPR_CIABR (0x0BB)
#define SPR_DAWRX (0x0BC)
#define SPR_HFSCR (0x0BE)
#define SPR_VRSAVE (0x100)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index cfb1bc088950..f88bdf7b3cd1 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7603,6 +7603,11 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_DAWRX, 0x00000000);
+ spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_CIABR, 0x00000000);
}
static void gen_spr_970_dbg(CPUPPCState *env)
--
2.1.4
- Re: [Qemu-devel] [PATCH 07/17] ppc: Better figure out if processor has HV mode, (continued)
[Qemu-devel] [PATCH 05/17] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV, Cédric Le Goater, 2016/03/14
[Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR,
Cédric Le Goater <=
[Qemu-devel] [PATCH 08/17] ppc: Add placeholder SPRs for DPDES and DHDES on P8, Cédric Le Goater, 2016/03/14
[Qemu-devel] [PATCH 09/17] ppc: SPURR & PURR are HV writeable and privileged, Cédric Le Goater, 2016/03/14