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Re: [Qemu-devel] [PATCH 15/17] ppc: Add dummy POWER8 MPPR register


From: Thomas Huth
Subject: Re: [Qemu-devel] [PATCH 15/17] ppc: Add dummy POWER8 MPPR register
Date: Wed, 16 Mar 2016 07:17:02 +0100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0

On 16.03.2016 02:14, David Gibson wrote:
> On Mon, Mar 14, 2016 at 05:56:38PM +0100, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt <address@hidden>
>>
>> Controls the micropartition prefetch, this is pretty much meaningless
>> in full emulation (used for priming the caches on real HW).
>>
>> Signed-off-by: Benjamin Herrenschmidt <address@hidden>
> 
> So, this is readable with HV=0, so technically a fix even for non-HV
> machines.  I'm guessing it's not actually read in practice outside the
> HV, though.  Not sure if this should go in 2.6 or 2.7.

Patch looks simple (i.e. without risk) enough to be fine for 2.6, I think.
But looking at this again, I wonder why there is no KVM_REG_PPC_*
definition for this register, so that it could be sync'ed with the
kernel, too? Is that on purpose or is it just missing by accident?

 Thomas

>> ---
>>  target-ppc/cpu.h            |  1 +
>>  target-ppc/translate_init.c | 13 +++++++++++++
>>  2 files changed, 14 insertions(+)
>>
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index 81a3e6b5ed29..5203cc6a3bfb 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -1398,6 +1398,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, 
>> bool ifetch)
>>  #define SPR_DHDES             (0x0B1)
>>  #define SPR_DPDES             (0x0B0)
>>  #define SPR_DAWR              (0x0B4)
>> +#define SPR_MPPR              (0x0B8)
>>  #define SPR_RPR               (0x0BA)
>>  #define SPR_DAWRX             (0x0BC)
>>  #define SPR_HFSCR             (0x0BE)
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index 28a9c2e73156..cfb1bc088950 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -8161,6 +8161,18 @@ static void gen_spr_power8_ic(CPUPPCState *env)
>>  #endif
>>  }
>>  
>> +static void gen_spr_power8_book4(CPUPPCState *env)
>> +{
>> +    /* Add a number of P8 book4 registers */
>> +#if !defined(CONFIG_USER_ONLY)
>> +    spr_register_hv(env, SPR_MPPR, "MPPR",
>> +                    SPR_NOACCESS, SPR_NOACCESS,
>> +                    &spr_read_generic, SPR_NOACCESS,
>> +                    &spr_read_generic, &spr_write_generic,
>> +                    0);
>> +#endif
>> +}
>> +
>>  static void init_proc_book3s_64(CPUPPCState *env, int version)
>>  {
>>      gen_spr_ne_601(env);
>> @@ -8216,6 +8228,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int 
>> version)
>>          gen_spr_power8_rpr(env);
>>          gen_spr_power8_dbell(env);
>>          gen_spr_power8_ic(env);
>> +        gen_spr_power8_book4(env);
>>      }
>>      if (version < BOOK3S_CPU_POWER8) {
>>          gen_spr_book3s_dbg(env);
> 


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