Re: [Qemu-devel] Timer interrupts for -M raspi2

[Antonio Huete Jiménez]

Hi Andrew,

Yeah, that's what I think. I believe I must be overlooking something  
but I just can't find what.

With regards to the ARM Generic timer, I have set the enable bit[0]  
for CNTP_CTL and also I've set CNTP_TVAL, that's why I think the  
interrupt is triggered on the real hardware.

I'm hoping anywone here can give me a hint on what I might be doing wrong.

In any case thanks a lot for your help and patience :-)

Best regards,
Antonio Huete

Andrew Baumann <address@hidden> escribió:

> Hi Antonio,
>
> > From: Antonio Huete Jiménez [mailto:address@hidden
> > Sent: Wednesday, 16 March 2016 4:24 PM
> >
> > Hi Andrew,
> >
> > I thought the timer that was not implemented was the local timer
> > (located at 0x40000034) and that the core timers interrupt control
> > registers starting at 0x40000040 were the per-core timers.
>
> Oh, sorry, you're right; I replied too quickly.
>
> Yes, that should work. Bits 0 and 3 are wired up to what qemu refers  
> to as GTIMER_PHYS and GTIMER_VIRT respectively. (The other two  
> timers aren't currently connected; I can't remember if that's  
> because they weren't modelled by core QEMU when I was implementing  
> the device model, or just because I wasn't sure how to route them  
> and never came back to fix it.)
>
> If you are seeing interrupts on real hardware and not on qemu, then  
> it may be because the board performs some additional setup that you  
> are relying on. I'm hardly an expert on ARM, but I would imagine you  
> need to also need to setup the timer's control and count registers  
> (using mcr/mrc) to get it ticking. The write to 0x40000040 simply  
> enables the interrupt.
>
> > Can you please point me to the documentation about this ARM per-core
> > timers?
>
> Here's a starting point to some docs (just from a quick search):
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438c/BGBBIJCB.html
>
> Cheers,
> Andrew
>
> > Andrew Baumann <address@hidden> escribió:
> >
> > > Hi Antonio,
> > >
> > >> From: Antonio Huete Jiménez [mailto:address@hidden
> > >> Sent: Wednesday, 16 March 2016 3:40 PM
> > >>
> > >> Hi,
> > >>
> > >> I am experiencing what I think it's an issue with -M raspi2 and
> > >> interrupts in a baremetal application.
> > >>
> > >> According to this document
> > >>
> > (https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2
> > >> 836/QA7_rev3.4.pdf), and if I understood it correctly, you can enable
> > timer
> > >> interrupts for core0 by setting bit 0 at 0x40000040 and you can trigger
> > them
> > >> by using the ARM Generic
> > >> Timer.
> > >>
> > >> With this procedure I can reliably trigger that timer interrupt in the
> > >> real hardware by setting CNTP_CTL and CNTP_TVAL but on qemu it
> > doesn't
> > >> seem to be triggered.
> > >>
> > >> Can somebody please tell me what I might be doing wrong?
> > >
> > > I don't think you're doing anything wrong; we just don't model this
> > > timer hardware yet (neither Linux nor Windows needs it). If you want
> > > to take a stab at adding it, the relevant hardware emulation is
> > > hw/intc/bcm2836_control.c.
> > >
> > > If you're willing to use different timer sources, then I suggest
> > > looking at the ARM per-core timers. I also have Gregory's emulation
> > > code for the other bcm2835 timers in my private github, and I hope
> > > to submit to upstream qemu after the current freeze, since it is
> > > needed for pi1 Linux support.
> > >
> > > Cheers,
> > > Andrew