[Qemu-devel] [PULL v2 17/21] target-mips: check CP0 enabled for CACHE instruction also in R6

[Leon Alrae]

Signed-off-by: Leon Alrae <address@hidden>
---
 target-mips/translate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index a5b8805..65f2caf 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -17194,6 +17194,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, 
DisasContext *ctx)
         /* Treat as NOP. */
         break;
     case R6_OPC_CACHE:
+        check_cp0_enabled(ctx);
         /* Treat as NOP. */
         break;
     case R6_OPC_SC:
-- 
2.1.0