Re: [Qemu-devel] [PATCH] target-ppc: Multiple/String Word alignment exception

[Thomas Huth]

On 31.03.2016 09:15, Alexander Graf wrote:
> 
> On 31.03.16 09:06, Laurent Vivier wrote:
>>
>> On 31/03/2016 08:54, Alexander Graf wrote:
>>>
>>> On 31.03.16 01:29, David Gibson wrote:
>>>> On Wed, 30 Mar 2016 19:13:00 +0200
>>>> Laurent Vivier <address@hidden> wrote:
>>>>
>>>>> If the processor is in little-endian mode, an alignment interrupt must
>>>>> occur for the following instructions: lmw, stmw, lswi, lswx, stswi or 
>>>>> stswx.
>>>>>
>>>>> This is what happens with KVM, so change TCG to do the same.
>>>>>
>>>>> As the instruction can be emulated by the kernel, enable the change
>>>>> only in softmmu mode.
>>>>>
>>>>> Signed-off-by: Laurent Vivier <address@hidden>
>>>>
>>>> I guess this makes sense given the existing hardware behaviour, even
>>>> though it seems a bit perverse to me to make the emulator strictly less
>>>> functional.
>>>>
>>>> Alex, what do you think?
>>>
>>> In general we only implement strict checks if it breaks guests not to
>>> have them. Are you aware of any such case?

Well, the new "emulator" test for kvm-unit-tests only works right if
this is done correctly ;-)

> That's basically what David was trying to say with POWER9. How do you
> know that POWER9 still requires strong alignment checks for indexed LE
> instructions? If it doesn't, we'd have to add a case in TCG to not the
> the checks again. These multiply very quickly :).

I'd agree with you in case something is not properly defined in the ISA
or marked as implementation specific. But in this case, this behavior is
properly documented in the PowerISA spec. IMHO, if something is
documented in the ISA, we should follow that behavior in QEMU, too, i.e.
add the alignment checks here. And if POWER9 is different, there must be
a new version of the PowerISA for this one day ... i.e. we have to make
adaptions for that anyway.

 Thomas