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[Qemu-devel] [RFC v8 04/14] softmmu: Simplify helper_*_st_name, wrap RA
From: |
Alvise Rigo |
Subject: |
[Qemu-devel] [RFC v8 04/14] softmmu: Simplify helper_*_st_name, wrap RAM code |
Date: |
Tue, 19 Apr 2016 15:39:21 +0200 |
Attempting to simplify the helper_*_st_name, wrap the code relative to a
RAM access into an inline function. The function covers both BE and LE cases
and it is expanded twice in each helper (TODO: check this last statement).
Suggested-by: Jani Kokkonen <address@hidden>
Suggested-by: Claudio Fontana <address@hidden>
CC: Alex Bennée <address@hidden>
Signed-off-by: Alvise Rigo <address@hidden>
---
softmmu_template.h | 80 +++++++++++++++++++++++++++---------------------------
1 file changed, 40 insertions(+), 40 deletions(-)
diff --git a/softmmu_template.h b/softmmu_template.h
index 9185486..ea6a0fb 100644
--- a/softmmu_template.h
+++ b/softmmu_template.h
@@ -433,13 +433,48 @@ static inline void
smmu_helper(do_mmio_store)(CPUArchState *env,
glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr);
}
+static inline void smmu_helper(do_ram_store)(CPUArchState *env,
+ bool little_endian, DATA_TYPE val,
+ target_ulong addr, TCGMemOpIdx oi,
+ unsigned mmu_idx, int index,
+ uintptr_t retaddr)
+{
+ uintptr_t haddr;
+
+ /* Handle slow unaligned access (it spans two pages or IO). */
+ if (DATA_SIZE > 1
+ && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
+ >= TARGET_PAGE_SIZE)) {
+ smmu_helper(do_unl_store)(env, little_endian, val, addr, oi, mmu_idx,
+ retaddr);
+ return;
+ }
+
+ /* Handle aligned access or unaligned access in the same page. */
+ if ((addr & (DATA_SIZE - 1)) != 0
+ && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
+ cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
+ mmu_idx, retaddr);
+ }
+
+ haddr = addr + env->tlb_table[mmu_idx][index].addend;
+#if DATA_SIZE == 1
+ glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
+#else
+ if (little_endian) {
+ glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
+ } else {
+ glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
+ }
+#endif
+}
+
void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
TCGMemOpIdx oi, uintptr_t retaddr)
{
unsigned mmu_idx = get_mmuidx(oi);
int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
- uintptr_t haddr;
/* Adjust the given return address. */
retaddr -= GETPC_ADJ;
@@ -465,27 +500,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong
addr, DATA_TYPE val,
return;
}
- /* Handle slow unaligned access (it spans two pages or IO). */
- if (DATA_SIZE > 1
- && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
- >= TARGET_PAGE_SIZE)) {
- smmu_helper(do_unl_store)(env, true, val, addr, oi, mmu_idx, retaddr);
- return;
- }
-
- /* Handle aligned access or unaligned access in the same page. */
- if ((addr & (DATA_SIZE - 1)) != 0
- && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
- cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
- mmu_idx, retaddr);
- }
-
- haddr = addr + env->tlb_table[mmu_idx][index].addend;
-#if DATA_SIZE == 1
- glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
-#else
- glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
-#endif
+ smmu_helper(do_ram_store)(env, true, val, addr, oi, mmu_idx, index,
+ retaddr);
}
#if DATA_SIZE > 1
@@ -495,7 +511,6 @@ void helper_be_st_name(CPUArchState *env, target_ulong
addr, DATA_TYPE val,
unsigned mmu_idx = get_mmuidx(oi);
int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
- uintptr_t haddr;
/* Adjust the given return address. */
retaddr -= GETPC_ADJ;
@@ -521,23 +536,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong
addr, DATA_TYPE val,
return;
}
- /* Handle slow unaligned access (it spans two pages or IO). */
- if (DATA_SIZE > 1
- && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
- >= TARGET_PAGE_SIZE)) {
- smmu_helper(do_unl_store)(env, false, val, addr, oi, mmu_idx, retaddr);
- return;
- }
-
- /* Handle aligned access or unaligned access in the same page. */
- if ((addr & (DATA_SIZE - 1)) != 0
- && (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
- cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
- mmu_idx, retaddr);
- }
-
- haddr = addr + env->tlb_table[mmu_idx][index].addend;
- glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
+ smmu_helper(do_ram_store)(env, false, val, addr, oi, mmu_idx, index,
+ retaddr);
}
#endif /* DATA_SIZE > 1 */
--
2.8.0
- [Qemu-devel] [RFC v8 00/14] Slow-path for atomic instruction translation, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 03/14] softmmu: Simplify helper_*_st_name, wrap MMIO code, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 05/14] softmmu: Add new TLB_EXCL flag, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 04/14] softmmu: Simplify helper_*_st_name, wrap RAM code,
Alvise Rigo <=
- [Qemu-devel] [RFC v8 01/14] exec.c: Add new exclusive bitmap to ram_list, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 06/14] qom: cpu: Add CPUClass hooks for exclusive range, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 09/14] softmmu: Honor the new exclusive bitmap, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 11/14] tcg: Create new runtime helpers for excl accesses, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 10/14] softmmu: Support MMIO exclusive accesses, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 08/14] softmmu: Add history of excl accesses, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 12/14] target-arm: translate: Use ld/st excl for atomic insns, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 02/14] softmmu: Simplify helper_*_st_name, wrap unaligned code, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 07/14] softmmu: Add helpers for a new slowpath, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 14/14] target-arm: aarch64: Use ls/st exclusive for atomic insns, Alvise Rigo, 2016/04/19