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[Qemu-devel] [RFC v8 13/14] target-arm: cpu64: use custom set_excl hook
From: |
Alvise Rigo |
Subject: |
[Qemu-devel] [RFC v8 13/14] target-arm: cpu64: use custom set_excl hook |
Date: |
Tue, 19 Apr 2016 15:39:30 +0200 |
In aarch64 the LDXP/STXP instructions allow to perform up to 128 bits
exclusive accesses. However, due to a softmmu limitation, such wide
accesses are not allowed.
To workaround this limitation, we need to support LoadLink instructions
that cover at least 128 consecutive bits (see the next patch for more
details).
Suggested-by: Jani Kokkonen <address@hidden>
Suggested-by: Claudio Fontana <address@hidden>
Signed-off-by: Alvise Rigo <address@hidden>
---
target-arm/cpu64.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index cc177bb..1d45e66 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -287,6 +287,13 @@ static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
}
}
+static void aarch64_set_excl_range(CPUState *cpu, hwaddr addr, hwaddr size)
+{
+ cpu->excl_protected_range.begin = addr;
+ /* At least cover 128 bits for a STXP access (two paired doublewords
case)*/
+ cpu->excl_protected_range.end = addr + 16;
+}
+
static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
@@ -297,6 +304,7 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void
*data)
cc->gdb_write_register = aarch64_cpu_gdb_write_register;
cc->gdb_num_core_regs = 34;
cc->gdb_core_xml_file = "aarch64-core.xml";
+ cc->cpu_set_excl_protected_range = aarch64_set_excl_range;
}
static void aarch64_cpu_register(const ARMCPUInfo *info)
--
2.8.0
- [Qemu-devel] [RFC v8 01/14] exec.c: Add new exclusive bitmap to ram_list, (continued)
- [Qemu-devel] [RFC v8 01/14] exec.c: Add new exclusive bitmap to ram_list, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 06/14] qom: cpu: Add CPUClass hooks for exclusive range, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 09/14] softmmu: Honor the new exclusive bitmap, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 11/14] tcg: Create new runtime helpers for excl accesses, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 10/14] softmmu: Support MMIO exclusive accesses, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 08/14] softmmu: Add history of excl accesses, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 12/14] target-arm: translate: Use ld/st excl for atomic insns, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 02/14] softmmu: Simplify helper_*_st_name, wrap unaligned code, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 07/14] softmmu: Add helpers for a new slowpath, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 14/14] target-arm: aarch64: Use ls/st exclusive for atomic insns, Alvise Rigo, 2016/04/19
- [Qemu-devel] [RFC v8 13/14] target-arm: cpu64: use custom set_excl hook,
Alvise Rigo <=