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[Qemu-devel] [PATCH 31/52] target-m68k: some bit ops cleanup
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PATCH 31/52] target-m68k: some bit ops cleanup |
Date: |
Wed, 4 May 2016 22:12:11 +0200 |
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/translate.c | 34 +++++++++++++++-------------------
1 file changed, 15 insertions(+), 19 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index cd656fe..817f0b3 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1300,39 +1300,36 @@ DISAS_INSN(bitop_reg)
else
opsize = OS_LONG;
op = (insn >> 6) & 3;
-
- gen_flush_flags(s);
-
SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
- src2 = DREG(insn, 9);
- dest = tcg_temp_new();
- tmp = tcg_temp_new();
+ gen_flush_flags(s);
+ src2 = tcg_temp_new();
if (opsize == OS_BYTE)
- tcg_gen_andi_i32(tmp, src2, 7);
+ tcg_gen_andi_i32(src2, DREG(insn, 9), 7);
else
- tcg_gen_andi_i32(tmp, src2, 31);
+ tcg_gen_andi_i32(src2, DREG(insn, 9), 31);
- src2 = tcg_const_i32(1);
- tcg_gen_shl_i32(src2, src2, tmp);
- tcg_temp_free(tmp);
+ tmp = tcg_const_i32(1);
+ tcg_gen_shl_i32(tmp, tmp, src2);
+ tcg_temp_free(src2);
- tcg_gen_and_i32(QREG_CC_Z, src1, src2);
+ tcg_gen_and_i32(QREG_CC_Z, src1, tmp);
+ dest = tcg_temp_new();
switch (op) {
case 1: /* bchg */
- tcg_gen_xor_i32(dest, src1, src2);
+ tcg_gen_xor_i32(dest, src1, tmp);
break;
case 2: /* bclr */
- tcg_gen_andc_i32(dest, src1, src2);
+ tcg_gen_andc_i32(dest, src1, tmp);
break;
case 3: /* bset */
- tcg_gen_or_i32(dest, src1, src2);
+ tcg_gen_or_i32(dest, src1, tmp);
break;
default: /* btst */
break;
}
- tcg_temp_free(src2);
+ tcg_temp_free(tmp);
if (op) {
DEST_EA(env, insn, opsize, dest, &addr);
}
@@ -1416,17 +1413,16 @@ DISAS_INSN(bitop_im)
return;
}
- gen_flush_flags(s);
-
SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
+ gen_flush_flags(s);
if (opsize == OS_BYTE)
bitnum &= 7;
else
bitnum &= 31;
mask = 1 << bitnum;
- tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
+ tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
if (op) {
tmp = tcg_temp_new();
--
2.5.5
- [Qemu-devel] [PATCH 26/52] target-m68k: Inline shifts, (continued)
- [Qemu-devel] [PATCH 26/52] target-m68k: Inline shifts, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 27/52] target-m68k: Inline addx, subx, negx, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 28/52] target-m68k: add addx/subx/negx ops, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 29/52] target-m68k: factorize flags computing, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 30/52] target-m68k: add scc/dbcc, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 31/52] target-m68k: some bit ops cleanup,
Laurent Vivier <=
- [Qemu-devel] [PATCH 32/52] target-m68k: bitfield ops, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 33/52] target-m68k: inline divu/divs, Laurent Vivier, 2016/05/04